Maths Demo

This folder accompanies the Project F series: Maths and Algorithms with FPGAs. These SystemVerilog maths demos let your visualize many of the concepts we cover. You can freely build on these MIT licensed designs. Have fun.

File layout:

• ice40 - designs for iCEBreaker and other Lattice iCE40UP boards
• xc7 - designs for Arty and other Xilinx 7 Series boards
• xc7-hd - designs for Nexys Video and larger Xilinx 7 Series FPGAs
• sim - simulation with Verilator and LibSDL; see the Simulation README

These designs make use of modules from the Project F library. Check the included iCE40 Makefile or Vivado create_project.tcl to see the list of modules.

Included demos:

• top_graphing - graph a mathematical function (uses DSPs for multiplication)

iCEBreaker Build

Designs for iCEBreaker are available but still need additional testing. Feel free to experiment with them.

Arty Build

To create a Vivado project for the Digilent Arty (original or A7-35T); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/maths/demo/xc7/vivado
source ./create_project.tcl

You can then build top_graphing etc. as you would for any Vivado project.

Other Xilinx 7 Series Boards

It's straightforward to adapt the project for other Xilinx 7 Series boards:

1. Create a suitable constraints file named <board>.xdc within the xc7 directory
2. Make a note of your board's FPGA part, such as xc7a35ticsg324-1L
3. Set the board and part names in Tcl, then source the create project script:

set board_name <board>
set fpga_part <fpga-part>
cd projf-explore/maths/demo/xc7/vivado
source ./create_project.tcl

Replace <board> and <fpga-part> with the actual board and part names.

Linting

If you have Verilator installed, you can run the linting shell script lint.sh to check the designs. Learn more from Verilog Lint with Verilator.

SystemVerilog?

These designs use a little SystemVerilog to make Verilog more pleasant. See the Library README for details of SV features used.