Match xsim implementation with RTL simulation

[xross]

The xsim based test suite passes with sub 540MHz core frequencies whereas on the real hardware some packet issues are experienced.

Some work should be done to compare RTL to xsim simulations and to ascertain if any delays etc are missing in the xsim implementation.

Some difference between xsim and real hardware is to be expected, but currently the error-bar is rather large.

[xross]

Considering HS first.

First notable difference is RxActive end delay. This drops with RxValid. Note this will be implementation specific, specification is not fixed.

Modifying RXA_END_DELAY in the testbench (from 2 to 0) resorts in test failures:

FAILED test_bulk_loopback.py::test_RunUsbSession[xs3-1-1-HS-4-600] - assert False
FAILED test_bulk_notready.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_bulk_rx_basic.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_bulk_rx_basic_badpid.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_bulk_rx_basic_nodata.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_bulk_rx_basic_badcrc32.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_bulk_rx_basic_rxerror.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_control_basic_set.py::test_RunUsbSession[xs3-0-1-HS-6-600] - assert False
FAILED test_iso_rx_basic.py::test_RunUsbSession[xs3-1-1-HS-6-600] - ValueError: list.remove(x): x not in list
FAILED test_ping_stall.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_stall_control.py::test_RunUsbSession[xs3-0-1-HS-6-600] - assert False
FAILED test_stall_basic.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
FAILED test_stall_epready.py::test_RunUsbSession[xs3-1-1-HS-6-600] - assert False
============================================================= 13 failed, 18 passed, 2 xfailed in 1067.69s (0:17:47) =============================================================

Note:

• modding RXA_END_DELAY from 2 to 1 results in no test failures.
• modding dummy threads from 6 to 4 (so 6 threads total) reduces failures to 2 (iso_rx_basic and ping_stall)

[xross]

Second notable different is RxActive start delay - RTL sim shows 5 cycles, xsim shows 6 (despite RXA_START_DELAY being set to 5...)

The off by one issue fixed here: 5e3d72e

Note, value of 0 is not achievable at the moment.

[xross]

It has been noted that the set_pad_delay() doesn't effect the value at the flag1 port in the xsim based testbench

Checking the RTL sim and looking inData[] in the RTL sim for Flag1 port (portInOut1Bit_inst4) and adjusting set_pad_delay() shows a delay being added. This appears to be an issue with the xsim implementation.

The pad-delay appears to be inserted between the port and the shim - not between the shim and the phy as might be expected.

The delay is only seen at inData at the port. Not i_UTMI_RXACTIVE into the shim or o_utmi_rx_flag2 out from the shim.

[xross]

Pad delay raised against xsim here: https://github0.xmos.com/xmos-int/xsim/issues/69