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Merge pull request #4974 from ARMmbed/release-candidate
Release candidate for mbed-os-5.5.6
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| Original file line number | Diff line number | Diff line change |
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| /* Copyright (c) 2009 - 2012 ARM LIMITED | ||
|
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| All rights reserved. | ||
| Redistribution and use in source and binary forms, with or without | ||
| modification, are permitted provided that the following conditions are met: | ||
| - Redistributions of source code must retain the above copyright | ||
| notice, this list of conditions and the following disclaimer. | ||
| - Redistributions in binary form must reproduce the above copyright | ||
| notice, this list of conditions and the following disclaimer in the | ||
| documentation and/or other materials provided with the distribution. | ||
| - Neither the name of ARM nor the names of its contributors may be used | ||
| to endorse or promote products derived from this software without | ||
| specific prior written permission. | ||
| * | ||
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
| ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE | ||
| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||
| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||
| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||
| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||
| POSSIBILITY OF SUCH DAMAGE. | ||
| ---------------------------------------------------------------------------*/ | ||
|
|
||
| /*---------------------------------------------------------------------------- | ||
| * Functions | ||
| *---------------------------------------------------------------------------*/ | ||
| .text | ||
| .global __v7_all_cache | ||
| /* | ||
| * __STATIC_ASM void __v7_all_cache(uint32_t op) { | ||
| */ | ||
| __v7_all_cache: | ||
| .arm | ||
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| PUSH {R4-R11} | ||
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| MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ | ||
| ANDS R3, R6, #0x07000000 /* Extract coherency level */ | ||
| MOV R3, R3, LSR #23 /* Total cache levels << 1 */ | ||
| BEQ Finished /* If 0, no need to clean */ | ||
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| MOV R10, #0 /* R10 holds current cache level << 1 */ | ||
| Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ | ||
| MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ | ||
| AND R1, R1, #7 /* Isolate those lower 3 bits */ | ||
| CMP R1, #2 | ||
| BLT Skip /* No cache or only instruction cache at this level */ | ||
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| MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ | ||
| ISB /* ISB to sync the change to the CacheSizeID reg */ | ||
| MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ | ||
| AND R2, R1, #7 /* Extract the line length field */ | ||
| ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ | ||
| LDR R4, =0x3FF | ||
| ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ | ||
| CLZ R5, R4 /* R5 is the bit position of the way size increment */ | ||
| LDR R7, =0x7FFF | ||
| ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ | ||
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| Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ | ||
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| Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ | ||
| ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ | ||
| CMP R0, #0 | ||
| BNE Dccsw | ||
| MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ | ||
| B cont | ||
| Dccsw: CMP R0, #1 | ||
| BNE Dccisw | ||
| MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ | ||
| B cont | ||
| Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ | ||
| cont: SUBS R9, R9, #1 /* Decrement the Way number */ | ||
| BGE Loop3 | ||
| SUBS R7, R7, #1 /* Decrement the Set number */ | ||
| BGE Loop2 | ||
| Skip: ADD R10, R10, #2 /* increment the cache number */ | ||
| CMP R3, R10 | ||
| BGT Loop1 | ||
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| Finished: | ||
| DSB | ||
| POP {R4-R11} | ||
| BX lr | ||
|
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| .END | ||
| /*---------------------------------------------------------------------------- | ||
| * end of file | ||
| *---------------------------------------------------------------------------*/ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,97 @@ | ||
| /* Copyright (c) 2009 - 2012 ARM LIMITED | ||
|
|
||
| All rights reserved. | ||
| Redistribution and use in source and binary forms, with or without | ||
| modification, are permitted provided that the following conditions are met: | ||
| - Redistributions of source code must retain the above copyright | ||
| notice, this list of conditions and the following disclaimer. | ||
| - Redistributions in binary form must reproduce the above copyright | ||
| notice, this list of conditions and the following disclaimer in the | ||
| documentation and/or other materials provided with the distribution. | ||
| - Neither the name of ARM nor the names of its contributors may be used | ||
| to endorse or promote products derived from this software without | ||
| specific prior written permission. | ||
| * | ||
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
| ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE | ||
| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||
| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||
| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||
| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||
| POSSIBILITY OF SUCH DAMAGE. | ||
| ---------------------------------------------------------------------------*/ | ||
|
|
||
| /*---------------------------------------------------------------------------- | ||
| * Functions | ||
| *---------------------------------------------------------------------------*/ | ||
| SECTION `.text`:CODE:NOROOT(2) | ||
| arm | ||
| PUBLIC __v7_all_cache | ||
| /* | ||
| * __STATIC_ASM void __v7_all_cache(uint32_t op) { | ||
| */ | ||
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| __v7_all_cache: | ||
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| PUSH {R4-R11} | ||
|
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| MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ | ||
| ANDS R3, R6, #0x07000000 /* Extract coherency level */ | ||
| MOV R3, R3, LSR #23 /* Total cache levels << 1 */ | ||
| BEQ Finished /* If 0, no need to clean */ | ||
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| MOV R10, #0 /* R10 holds current cache level << 1 */ | ||
| Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ | ||
| MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ | ||
| AND R1, R1, #7 /* Isolate those lower 3 bits */ | ||
| CMP R1, #2 | ||
| BLT Skip /* No cache or only instruction cache at this level */ | ||
|
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| MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ | ||
| ISB /* ISB to sync the change to the CacheSizeID reg */ | ||
| MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ | ||
| AND R2, R1, #7 /* Extract the line length field */ | ||
| ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ | ||
| LDR R4, =0x3FF | ||
| ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ | ||
| CLZ R5, R4 /* R5 is the bit position of the way size increment */ | ||
| LDR R7, =0x7FFF | ||
| ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ | ||
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| Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ | ||
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| Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ | ||
| ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ | ||
| CMP R0, #0 | ||
| BNE Dccsw | ||
| MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ | ||
| B cont | ||
| Dccsw: CMP R0, #1 | ||
| BNE Dccisw | ||
| MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ | ||
| B cont | ||
| Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ | ||
| cont: SUBS R9, R9, #1 /* Decrement the Way number */ | ||
| BGE Loop3 | ||
| SUBS R7, R7, #1 /* Decrement the Set number */ | ||
| BGE Loop2 | ||
| Skip: ADD R10, R10, #2 /* increment the cache number */ | ||
| CMP R3, R10 | ||
| BGT Loop1 | ||
|
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| Finished: | ||
| DSB | ||
| POP {R4-R11} | ||
| BX lr | ||
|
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||
|
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||
| END | ||
| /*---------------------------------------------------------------------------- | ||
| * end of file | ||
| *---------------------------------------------------------------------------*/ | ||
|
|
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26 changes: 26 additions & 0 deletions
26
...ures/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/lwipopts_conf.h
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,26 @@ | ||
| /* | ||
| * Copyright (c) 2012-2015, ARM Limited, All Rights Reserved | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| * | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); you may | ||
| * not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT | ||
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| */ | ||
|
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| #ifndef LWIPOPTS_CONF_H | ||
| #define LWIPOPTS_CONF_H | ||
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| #define LWIP_TRANSPORT_ETHERNET 1 | ||
| #define ETH_PAD_SIZE 2 | ||
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| #define MEM_SIZE (16*1024)//(8*1024)//(16*1024) | ||
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| #endif |
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