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[STM32F3xx] CAN development for STM32F3xx family #1762

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merged 5 commits into from
Jun 3, 2016
Merged

[STM32F3xx] CAN development for STM32F3xx family #1762

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7876749
Added CAN API for STM32F3xx family
BartSX Apr 19, 2016
656d195
[NUCLEO_F334R8] Added CAN support
BartSX Apr 19, 2016
9a78b01
[NUCLEO_F303RE] Added CAN support
BartSX Apr 19, 2016
347a5e6
[NUCLEO_F303K8] Added CAN support
BartSX Apr 19, 2016
f1c42bf
[NUCLEO_F302R8] Added CAN support
BartSX Apr 19, 2016
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2 changes: 1 addition & 1 deletion hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/stm32f302x8.h
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Expand Up @@ -792,7 +792,7 @@ typedef struct
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define CAN1 ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
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2 changes: 1 addition & 1 deletion hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/stm32f303x8.h
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Expand Up @@ -758,7 +758,7 @@ typedef struct
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define CAN1 ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
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2 changes: 1 addition & 1 deletion hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/stm32f303xe.h
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Expand Up @@ -924,7 +924,7 @@ typedef struct
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define CAN1 ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
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2 changes: 1 addition & 1 deletion hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/stm32f334x8.h
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Expand Up @@ -872,7 +872,7 @@ typedef struct
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define CAN1 ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
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4 changes: 4 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/PeripheralPins.h
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Expand Up @@ -63,4 +63,8 @@ extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[];

//*** CAN ***
extern const PinMap PinMap_CAN_RD[];
extern const PinMap PinMap_CAN_TD[];

#endif
4 changes: 4 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralNames.h
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Expand Up @@ -73,6 +73,10 @@ typedef enum {
PWM_17 = (int)TIM17_BASE
} PWMName;

typedef enum {
CAN_1 = (int)CAN_BASE
} CANName;

#ifdef __cplusplus
}
#endif
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12 changes: 12 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralPins.c
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Expand Up @@ -204,3 +204,15 @@ const PinMap PinMap_SPI_SSEL[] = {
{PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_RD[] = {
// {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, // Not available in 32 pins package
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_TD[] = {
// {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, // Not available in 32 pins package
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};
2 changes: 2 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h
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Expand Up @@ -54,6 +54,8 @@

#define DEVICE_SLEEP 1

#define DEVICE_CAN 1

//=======================================

#define DEVICE_SEMIHOST 0
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5 changes: 5 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h
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Expand Up @@ -106,6 +106,11 @@ struct pwmout_s {
uint32_t inverted;
};

struct can_s {
CANName can;
int index;
};

#include "gpio_object.h"

#ifdef __cplusplus
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4 changes: 4 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralNames.h
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Expand Up @@ -72,6 +72,10 @@ typedef enum {
PWM_17 = (int)TIM17_BASE
} PWMName;

typedef enum {
CAN_1 = (int)CAN_BASE
} CANName;

#ifdef __cplusplus
}
#endif
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10 changes: 10 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralPins.c
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Expand Up @@ -169,3 +169,13 @@ const PinMap PinMap_SPI_SSEL[] = {
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_RD[] = {
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_TD[] = {
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};
2 changes: 2 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h
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Expand Up @@ -54,6 +54,8 @@

#define DEVICE_SLEEP 1

#define DEVICE_CAN 1

//=======================================

#define DEVICE_SEMIHOST 0
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5 changes: 5 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h
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Expand Up @@ -106,6 +106,11 @@ struct pwmout_s {
uint32_t inverted;
};

struct can_s {
CANName can;
int index;
};

#include "gpio_object.h"

#ifdef __cplusplus
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4 changes: 4 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h
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Expand Up @@ -82,6 +82,10 @@ typedef enum {
PWM_17 = (int)TIM17_BASE
} PWMName;

typedef enum {
CAN_1 = (int)CAN_BASE
} CANName;

#ifdef __cplusplus
}
#endif
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12 changes: 12 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralPins.c
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Expand Up @@ -255,3 +255,15 @@ const PinMap PinMap_SPI_SSEL[] = {
{PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_RD[] = {
{PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_TD[] = {
{PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};
2 changes: 2 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h
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Expand Up @@ -54,6 +54,8 @@

#define DEVICE_SLEEP 1

#define DEVICE_CAN 1

//=======================================

#define DEVICE_SEMIHOST 0
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5 changes: 5 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h
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Expand Up @@ -106,6 +106,11 @@ struct pwmout_s {
uint32_t inverted;
};

struct can_s {
CANName can;
int index;
};

#include "gpio_object.h"

#ifdef __cplusplus
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4 changes: 4 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralNames.h
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Expand Up @@ -73,6 +73,10 @@ typedef enum {
PWM_17 = (int)TIM17_BASE
} PWMName;

typedef enum {
CAN_1 = (int)CAN_BASE
} CANName;

#ifdef __cplusplus
}
#endif
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12 changes: 12 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralPins.c
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Expand Up @@ -210,3 +210,15 @@ const PinMap PinMap_SPI_SSEL[] = {
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_RD[] = {
{PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};

const PinMap PinMap_CAN_TD[] = {
{PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};
2 changes: 2 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h
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Expand Up @@ -54,6 +54,8 @@

#define DEVICE_SLEEP 1

#define DEVICE_CAN 1

//=======================================

#define DEVICE_SEMIHOST 0
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5 changes: 5 additions & 0 deletions hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h
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Expand Up @@ -106,6 +106,11 @@ struct pwmout_s {
uint32_t inverted;
};

struct can_s {
CANName can;
int index;
};

#include "gpio_object.h"

#ifdef __cplusplus
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