All test passed

Bohan-hu · Oct 24, 2020 · 091ae64 · 091ae64
1 parent 287f414
commit 091ae64
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Showing 4 changed files with 11 additions and 10 deletions.
diff --git a/src/main/scala/common/ram.scala b/src/main/scala/common/ram.scala
@@ -73,9 +73,9 @@ class SyncReadWriteMem extends Module {
   }.otherwise {
     ack := false.B
   }
-  ram.io.rIdx := io.mem2dmem.memAddr(63, 3)
+  ram.io.rIdx := Mux(io.mem2dmem.memAddr(63, 3) < 16777216.U, io.mem2dmem.memAddr(63, 3), 0.U)
   io.mem2dmem.memRdata := ram.io.rdata
-  ram.io.wIdx := io.mem2dmem.memAddr(63, 3)
+  ram.io.wIdx := Mux(io.mem2dmem.memAddr(63, 3) < 16777216.U, io.mem2dmem.memAddr(63, 3), 0.U)
   ram.io.wdata := io.mem2dmem.memWdata
   ram.io.wmask := io.mem2dmem.memWmask
   ram.io.wen := io.mem2dmem.memWen

diff --git a/src/main/scala/core/exu.scala b/src/main/scala/core/exu.scala
@@ -99,9 +99,10 @@ class EXU extends Module {
   // Load / Store instruction
   // Can be exceptions
   val mem = Module(new MEM)
-  io.toclint := mem.io.toclint
-  io.mem2dmem := mem.io.mem2dmem
-  mem.io.isMemOp := io.decode2Exe.isMemOp
+  io.toclint <> mem.io.toclint
+  io.mem2dmem <> mem.io.mem2dmem
+  mem.io.MemType := io.decode2Exe.MemType
+  mem.io.isMemOp := io.decode2Exe.isMemOp & io.instBundleIn.instValid
   mem.io.MemOp := io.decode2Exe.MemOp
   mem.io.baseAddr := op1
   mem.io.imm := op2

diff --git a/src/main/scala/core/mem.scala b/src/main/scala/core/mem.scala
@@ -155,10 +155,10 @@ class MEM extends Module {
   }
 
   // No prior Exception happens, and the op type is read, notice the signal is for dmem
-  val memRead = io.isMemOp & io.MemOp === MEM_READ & !isMMIO & !io.exceInfoIn.valid
+  val memRead = io.isMemOp & io.MemOp === MEM_READ & !io.exceInfoIn.valid
 
-  io.mem2dmem.memRreq := memRead
-  val memPending = !io.mem2dmem.memRvalid & memRead
+  io.mem2dmem.memRreq := memRead & !isMMIO
+  val memPending = !io.mem2dmem.memRvalid & io.mem2dmem.memRreq
   when(memRead) {
 //    printf("memRAddr = 0x%x, memRdata = 0x%x\n", io.exe2Mem.aluResult, memRdata)
   }
@@ -196,7 +196,7 @@ class MEM extends Module {
   io.mem2dmem.memAddr := accessPAddr
   io.mem2dmem.memWdata := DataTypesUtils.WDataGen(dataSize, accessVAddr, io.R2Val)
   io.mem2dmem.memWmask := DataTypesUtils.Byte2BitMask(DataTypesUtils.ByteMaskGen(dataSize, accessVAddr))
-  io.mem2dmem.memWen := memWrite
+  io.mem2dmem.memWen := memWrite & !isMMIO
   io.memResult := Mux(signExt, memRdataRawExt, memRdataRaw)
   io.pauseReq := memPending
 

diff --git a/src/main/scala/core/top.scala b/src/main/scala/core/top.scala
@@ -28,7 +28,7 @@ class Top extends Module {
   ifu.io.rdata := imem.io.rdata
   ifu.io.branchRedir := exu.io.exe2IF
   ifu.io.exceptionRedir := csrFile.io.ifRedir
-  ifu.io.pause := exu.io.pauseReq  // Todo: Modify as 5 stage pipeline
+  ifu.io.pause := exu.io.pauseReq
 
   // IFU <> DECODER
   decoder.io.instBundleIn := ifu.io.inst_out