Mark tVal as a bug

src/main/scala/core/csrFile.scala

@@ -571,7 +571,7 @@ class CSRFile extends Module {
       mcause := io.commitCSR.exceptionInfo.cause
       mepc := io.commitCSR.exceptionInfo.epc
       mtval := Mux(io.commitCSR.exceptionInfo.cause(63) ||
-        io.commitCSR.exceptionInfo.cause === ExceptionNo.illegalInstr.U ||
+        io.commitCSR.exceptionInfo.cause === ExceptionNo.illegalInstr.U ||    // TODO: Wrong Implementation in Nutshell and Nemu
         io.commitCSR.exceptionInfo.cause === ExceptionNo.breakPoint.U ||
         io.commitCSR.exceptionInfo.cause === ExceptionNo.ecallM.U ||
         io.commitCSR.exceptionInfo.cause === ExceptionNo.ecallS.U ||
@@ -584,7 +584,7 @@ class CSRFile extends Module {
       scause := io.commitCSR.exceptionInfo.cause
       sepc := io.commitCSR.exceptionInfo.epc
       stval := Mux(io.commitCSR.exceptionInfo.cause(63) ||
-        io.commitCSR.exceptionInfo.cause === ExceptionNo.illegalInstr.U ||
+        io.commitCSR.exceptionInfo.cause === ExceptionNo.illegalInstr.U || // TODO: Wrong Implementation in Nutshell and Nemu
         io.commitCSR.exceptionInfo.cause === ExceptionNo.breakPoint.U ||
         io.commitCSR.exceptionInfo.cause === ExceptionNo.ecallM.U ||
         io.commitCSR.exceptionInfo.cause === ExceptionNo.ecallS.U ||

src/main/scala/core/pipelineCtrl.scala

@@ -0,0 +1,47 @@
+package core
+import chisel3._
+
+class PipelineRegCtrl extends Bundle {
+    val flush = Bool()
+    val hold = Bool()
+}
+
+class PipelineCtrlReq extends Bundle {
+    val flush = Bool()
+    val hold = Bool()
+}
+
+class PipelineCtrlIO extends Bundle {
+    val toIFID = Output(new PipelineRegCtrl)
+    val toIDEX = Output(new PipelineRegCtrl)
+    val toEXWB = Output(new PipelineRegCtrl)
+    val fromEX = Input(new PipelineCtrlReq)
+    val fromWB = Input(new PipelineCtrlReq)
+}
+
+// IFU's hold and flush be handled by redir from FU
+// EXU's flush be handled by its own fsm
+
+class PipelineCtrl extends Module {
+    val io = IO(new PipelineCtrlIO)
+    // Handle the flush request from WB, EX
+    when(io.fromEX.flush) {
+        io.toIFID.flush := true.B
+        io.toIDEX.flush := true.B
+    }
+    when(io.fromWB.flush) {
+        io.toIFID.flush := true.B
+        io.toIDEX.flush := true.B
+        // We need to handle the flush to FU: MDU, LSU, when flush comes, don't start the fsm
+        io.toEXWB.flush := true.B
+    }
+
+    when(io.fromEX.hold) {
+        io.toIFID.hold := true.B
+        io.toIDEX.hold := true.B
+    }
+    when(io.fromWB.flush) {
+        io.toIFID.flush := true.B
+        io.toIDEX.flush := true.B
+    }
+}