Connect LSU

src/main/scala/core/lsu.scala

@@ -3,24 +3,43 @@ package core
 import chisel3._
 import chisel3.util.Decoupled
 import defines._
-
+import mmu.DMEMReq
+import mmu._
+import chisel3.stage.ChiselStage
 class MemReq extends Bundle {
   val addr = UInt(64.W)
   val mask = UInt(8.W)
   val bytes = UInt(3.W)
   val isStore = Bool()
 }
 
+// A wrapper module 
 class LSUIO extends Bundle {
-  val srcA = Input(UInt(64.W))
-  val srcB = Input(UInt(64.W))
-  val ext_Imm = Input(UInt(64.W))
-  val addrOut = Input(UInt(64.W))
-  val memReq = Decoupled(new MemReq)
-  val memResp = Decoupled(UInt(64.W))
+  val memIO = new MEMIO
+  val ptwIO = new PTWIO
+  val lsu2Dmem = new MEM2dmem
 }
 
 class LSU extends Module {
-  val io = new LSUIO()
+  val io = IO(new LSUIO())
+  val mem = Module(new MEM)
+  val dptw = Module(new PTW(isDPTW = true))
+  mem.io <> io.memIO
+  dptw.io <> io.ptwIO
+  val memio = mem.io.mem2dmem
+  val ptwio = dptw.io.memReq
+  io.lsu2Dmem.memRreq := memio.memRreq | ptwio.memRreq
+  io.lsu2Dmem.memWdata := memio.memWdata
+  io.lsu2Dmem.memWen := memio.memWen
+  io.lsu2Dmem.memWmask := memio.memWmask
+  memio.memWrDone := io.lsu2Dmem.memWrDone
+  io.lsu2Dmem.memAddr := Mux(ptwio.memRreq, ptwio.memAddr, memio.memAddr)
+  memio.memRvalid := io.lsu2Dmem.memRvalid
+  ptwio.memRvalid := io.lsu2Dmem.memRvalid
+  ptwio.memWrDone := false.B
+}
 
+object LSU extends App {
+  val stage = new ChiselStage
+  stage.emitVerilog(new LSU)
 }

src/main/scala/mmu/ptw.scala

@@ -2,6 +2,7 @@ package mmu
 
 import chisel3._
 import chisel3.util._
+import _root_.core.MEM2dmem
 
 class PTE extends Bundle {
   val reversed = UInt(10.W)
@@ -46,7 +47,7 @@ class PTWIO extends Bundle {
   val satp_PPN = Input(UInt(44.W))
   val mxr = Input(Bool())
   // DMem request
-  val memReq = new DMEMReq
+  val memReq = new MEM2dmem
   // TODO: TLB Query
   val tlbQuery = Flipped(new TLBQuery)
   // TODO: TLB Update
@@ -64,11 +65,15 @@ class PTW(isDPTW: Boolean) extends Module {
   val isGlobalMappingReg = Reg(Bool())
   val pteReg             = Reg(UInt(64.W)).asTypeOf(new PTE)
   io.respValid           := false.B
-  io.memReq.rreq         := false.B
+  io.memReq.memRreq      := false.B
   io.pageFault           := false.B
   io.busy                := stateReg =/= sIDLE
   io.tlbQuery.vaddr      := io.reqVAddr
   io.respPaddr           := 0.U
+  io.memReq.memWdata     := 0.U
+  io.memReq.memWen       := 0.U
+  io.memReq.memWmask     := 0.U
+  io.memReq.memAddr      := ptrReg
   // TODO: Handle SUM
   // If TLB hit, stay in IDLE mode
   // Also need to consider whether the Sv39 translation is enabled
@@ -97,13 +102,13 @@ class PTW(isDPTW: Boolean) extends Module {
       }
     }
     is(sWAIT_PTE_Entry) {
-      io.memReq.rreq := true.B
+      io.memReq.memRreq := true.B
       when(io.flush) {
         stateReg := sWAIT_AFTER_FLUSH
       }
-      when(io.memReq.rvalid) {
+      when(io.memReq.memRvalid) {
         stateReg := sHANDLE_PTE_Entry
-        pteReg := io.memReq.rdata.asTypeOf(new PTE)
+        pteReg := io.memReq.memRdata.asTypeOf(new PTE)
       }
     }
     is(sHANDLE_PTE_Entry) {
@@ -185,7 +190,7 @@ class PTW(isDPTW: Boolean) extends Module {
       }
     }
     is(sWAIT_AFTER_FLUSH) { // Recover from a flush
-      when(io.memReq.rvalid) {
+      when(io.memReq.memRvalid) {
         stateReg := sIDLE
         pteLevelReg := 1.U
       }