Boot xv6

Bohan-hu · Oct 31, 2020 · 6f8c7a3 · 6f8c7a3
1 parent 3aa1688
commit 6f8c7a3
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Showing 4 changed files with 13 additions and 2 deletions.
diff --git a/src/main/scala/core/csrFile.scala b/src/main/scala/core/csrFile.scala
@@ -289,6 +289,7 @@ class CSRMMU extends Bundle {
 class commitCSR extends Bundle {
   val instValid = Input(Bool())
   val inst = Input(UInt(32.W))
+  val instPC = Input(UInt(64.W))
   val csrWData = Input(UInt(64.W))
   val csrAddr = Input(UInt(12.W))
   val csrOp = Input(UInt(3.W))
@@ -578,6 +579,7 @@ class CSRFile extends Module {
   // TODO: Consider MPRV Bit
   val isMret = io.commitCSR.inst === "b00110000001000000000000001110011".U
   val isSret = io.commitCSR.inst === "b00010000001000000000000001110011".U
+  val isSFence = io.commitCSR.inst === BitPat("b0001001??????????000000001110011")
   val isEret = isMret | isSret
   // ================== ERET Handler Begins ===================
   /*
@@ -655,6 +657,9 @@ class CSRFile extends Module {
   }.elsewhen(io.commitCSR.exceptionInfo.valid  && io.commitCSR.instValid ) {
     io.ifRedir.redir := true.B
     io.ifRedir.redirPC := handlerEntry
+  }.elsewhen(isSFence && io.commitCSR.instValid ) {
+    io.ifRedir.redir := true.B
+    io.ifRedir.redirPC := io.commitCSR.instPC + 4.U
   }
 }
 

diff --git a/src/main/scala/core/mem.scala b/src/main/scala/core/mem.scala
@@ -292,6 +292,9 @@ class MEM extends Module {
     is(sWAIT_WR) {
         io.mem2dmem.memWen := true.B
         io.pauseReq := true.B
+        when(io.mem2dmem.memWdata === 0x00000597.U ) {
+          printf("Writing Instruction to %x\n", io.mem2dmem.memAddr)
+        }
         when(io.mem2dmem.memWrDone) {
           io.pauseReq := false.B
           state := sIDLE
@@ -306,7 +309,7 @@ class MEM extends Module {
   // MMIO Flag
   BoringUtils.addSource(RegNext(io.isMemOp & isMMIO), "difftestIsMMIO")
   when(accessVAddr === 0x807FF000L.U & isStore) {
-    printf("Writing to &SATP: %x\n", io.R2Val)
+    // printf("Writing to &SATP: %x\n", io.R2Val)
   }
   // LSU 
   // IDLE -> ReqPADDR -> OP -> IDLE

diff --git a/src/main/scala/core/wb.scala b/src/main/scala/core/wb.scala
@@ -18,6 +18,7 @@ class WBIO extends Bundle {
 class WB extends Module {
   val io = IO(new WBIO)
   io.csrRw.exceptionInfo := io.exe2Commit.exceInfo
+  io.csrRw.instPC := io.instBundleIn.inst_pc
   BoringUtils.addSource(RegNext(io.instBundleIn.instValid), "difftestCommit")
   BoringUtils.addSource(RegNext(Mux(io.exe2Commit.exceInfo.valid & io.instBundleIn.instValid, io.exe2Commit.exceInfo.cause,0.U)),"difftestIntrNO")
   io.csrRw.csrWData := io.exe2Commit.arithResult

diff --git a/src/main/scala/mmu/ptw.scala b/src/main/scala/mmu/ptw.scala
@@ -163,7 +163,9 @@ class PTW(isDPTW: Boolean) extends Module {
             Attempting to fetch an instruction from a page that does not have execute permissions
             raises a fetch page-fault exception
              */
-            when(!pteConverted.X || !pteConverted.A) { // Instr, not eXecutable
+            // TODO: Recover the condition
+            // when(!pteConverted.X || !pteConverted.A) { // Instr, not eXecutable
+            when(!pteConverted.X) { // Instr, not eXecutable
               stateReg := sERROR
             }.otherwise {
               io.respValid := true.B