Delete TODOs

Bohan-hu · Dec 4, 2020 · 70d8b81 · 70d8b81
1 parent 683e9f8
commit 70d8b81
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Showing 7 changed files with 2 additions and 12 deletions.
diff --git a/src/main/scala/common/Consts.scala b/src/main/scala/common/Consts.scala
@@ -2,8 +2,6 @@ package common {
 
   import chisel3._
 
-  // TODO: Use enum to replace the constants
-  // TODO: Use zip to replace the xx :: xx :: xx style assignment (Think of a list of signal)
   object OpConstants {
 
     //************************************

diff --git a/src/main/scala/core/csrFile.scala b/src/main/scala/core/csrFile.scala
@@ -495,9 +495,8 @@ class CSRFile extends Module {
   }
   BoringUtils.addSource(mstatus & sstatus_read_mask.asUInt(), "difftestSstatus")
 
-  val WrMaskedCSR = Map( // TODO: Finish the CSR Mask
+  val WrMaskedCSR = Map(
     CSRAddr.mstatus -> mstatus_write_mask,
-    // CSRAddr.mip -> 0.U, // TODO: Patch: Unwritable
     CSRAddr.mideleg -> midelegMask, // SSIP, SEIP, STIP
     CSRAddr.mie -> ((1.U << 1) | (1.U << 3) | (1.U << 5) | (1.U << 7) | (1.U << 9) | (1.U << 11)),
     CSRAddr.mip -> "h77f".U,

diff --git a/src/main/scala/core/exu.scala b/src/main/scala/core/exu.scala
@@ -54,7 +54,6 @@ class EXUIO extends Bundle {
 
 class EXU extends Module {
   val io = IO(new EXUIO)
-  // TODO: Deal with the bypass condition
   val op1 = io.decode2Exe.Op1
   val op2 = io.decode2Exe.Op2
   val rs2 = io.decode2Exe.R2val

diff --git a/src/main/scala/core/ifu.scala b/src/main/scala/core/ifu.scala
@@ -38,7 +38,7 @@ class IFU extends Module {
   val state = RegInit(sIDLE)
   val pendingRedirect = RegInit(false.B)
   val pendingRedirectAddr = RegInit(0.U(64.W))
-  val pc = RegInit(0x80000000L.U(64.W)-4.U)
+  val pc = RegInit(0x40000000L.U(64.W)-4.U)
   val thisInstValid = WireInit(false.B)
   val thisPC = WireInit(0.U)
   val thisInst = WireInit(0.U)

diff --git a/src/main/scala/core/top.scala b/src/main/scala/core/top.scala
@@ -69,7 +69,6 @@ class Top extends Module {
   // io.instBundleOut := wb.io.instBundleOut
 
   // Consts
-  // TODO: TEST
   val clint = Module(new CLINT)
   csrFile.io.clintIn := clint.io.tocsr
   clint.io.memport <> axiBridge.io.toClint

diff --git a/src/main/scala/mmu/mmu.scala b/src/main/scala/mmu/mmu.scala
@@ -22,7 +22,6 @@ class MMUIO extends Bundle {
 
 class MMU (isDMMU: Boolean) extends Module {
   val io = IO(new MMUIO)
-  // TODO： Add TLB Here
   val tlb = Module(new TLB)
   val ptw = Module(new PTW(isDMMU))
   // PTW <> MMU

diff --git a/src/main/scala/mmu/ptw.scala b/src/main/scala/mmu/ptw.scala
@@ -48,9 +48,7 @@ class PTWIO extends Bundle {
   val mxr = Input(Bool())
   // DMem request
   val memReq = new NaiveBusM2S
-  // TODO: TLB Query
   val tlbQuery = Flipped(new TLBQuery)
-  // TODO: TLB Update
    val tlbUpdate = Output(new TLBEntry)
 
   // TODO: PMP Access Exception
@@ -187,7 +185,6 @@ class PTW(isDPTW: Boolean) extends Module {
               io.respValid := false.B
               stateReg := sERROR
             }
-            // TODO: Recover the condition
             when(!pteConverted.A ||
               (io.reqIsStore && !pteConverted.D)) { // pte.a = 0,
               // or if the memory access is a store and pte.d = 0
@@ -199,7 +196,6 @@ class PTW(isDPTW: Boolean) extends Module {
             Attempting to fetch an instruction from a page that does not have execute permissions
             raises a fetch page-fault exception
              */
-            // TODO: Recover the condition
             when(!pteConverted.X || !pteConverted.A) { // Instr, not eXecutable
             // when(!pteConverted.X) { // Instr, not eXecutable
               io.respValid := false.B