fix exception handle for misaligned superpage

Bohan-hu · Nov 24, 2020 · a6fb2ed · a6fb2ed
1 parent ab48048
commit a6fb2ed
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Showing 4 changed files with 8 additions and 9 deletions.
diff --git a/project/metals.sbt b/project/metals.sbt
@@ -1,4 +1,4 @@
 // DO NOT EDIT! This file is auto-generated.
 // This file enables sbt-bloop to create bloop config files.
 
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.4-13-408f4d80")
+addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.5-6-4768184c")
diff --git a/project/project/metals.sbt b/project/project/metals.sbt
@@ -1,4 +1,4 @@
 // DO NOT EDIT! This file is auto-generated.
 // This file enables sbt-bloop to create bloop config files.
 
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.4-13-408f4d80")
+addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.5-6-4768184c")
diff --git a/project/project/project/metals.sbt b/project/project/project/metals.sbt
@@ -1,4 +1,4 @@
 // DO NOT EDIT! This file is auto-generated.
 // This file enables sbt-bloop to create bloop config files.
 
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.4-13-408f4d80")
+addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.5-6-4768184c")
diff --git a/src/main/scala/mmu/ptw.scala b/src/main/scala/mmu/ptw.scala
@@ -203,12 +203,11 @@ class PTW(isDPTW: Boolean) extends Module {
           }
           // 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned superpage; stop and raise a page-fault
           // exception.
-          // TODO: Fix it
-          // when((pteLevelReg === 1.U && Cat(pteConverted.ppn2, pteConverted.ppn1) =/= 0.U) ||
-          //   (pteLevelReg === 2.U && pteConverted.ppn1 =/= 0.U)) {
-          //   io.respValid := false.B
-          //   stateReg := sERROR
-          // }
+          when((pteLevelReg === 1.U && Cat(pteConverted.ppn1, pteConverted.ppn0) =/= 0.U) ||
+            (pteLevelReg === 2.U && pteConverted.ppn0 =/= 0.U)) {
+            io.respValid := false.B
+            stateReg := sERROR
+          }
         }.otherwise { // the PTE is a pointer to the next level of the page table
           stateReg := sWAIT_PTE_Entry
           when(pteLevelReg === 1.U) {