Checkpoint: Can run rtt

Bohan-hu · Oct 24, 2020 · edacc84 · edacc84
1 parent ab22751
commit edacc84
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Showing 2 changed files with 84 additions and 50 deletions.
diff --git a/src/main/scala/common/Instructions.scala b/src/main/scala/common/Instructions.scala
@@ -5,10 +5,10 @@ import chisel3.util._
 
 object Instructions {
   // Loads
-  val LB = BitPat("b?????????????????000?????0000011")
-  val LH = BitPat("b?????????????????001?????0000011")
-  val LW = BitPat("b?????????????????010?????0000011")
-  val LD = BitPat("b?????????????????011?????0000011")
+  val LB  = BitPat("b?????????????????000?????0000011")
+  val LH  = BitPat("b?????????????????001?????0000011")
+  val LW  = BitPat("b?????????????????010?????0000011")
+  val LD  = BitPat("b?????????????????011?????0000011")
   val LBU = BitPat("b?????????????????100?????0000011")
   val LHU = BitPat("b?????????????????101?????0000011")
   val LWU = BitPat("b?????????????????110?????0000011")
@@ -20,77 +20,77 @@ object Instructions {
   val SD = BitPat("b?????????????????011?????0100011")
 
   // Shifts
-  val SLL = BitPat("b0000000??????????001?????0110011")
-  val SLLW = BitPat("b0000000??????????001?????0111011")
-  val SLLI = BitPat("b000000???????????001?????0010011")
+  val SLL   = BitPat("b0000000??????????001?????0110011")
+  val SLLW  = BitPat("b0000000??????????001?????0111011")
+  val SLLI  = BitPat("b000000???????????001?????0010011")
   val SLLIW = BitPat("b0000000??????????001?????0011011")
-  val SRL = BitPat("b0000000??????????101?????0110011")
-  val SRLW = BitPat("b0000000??????????101?????0111011")
-  val SRLI = BitPat("b000000???????????101?????0010011")
+  val SRL   = BitPat("b0000000??????????101?????0110011")
+  val SRLW  = BitPat("b0000000??????????101?????0111011")
+  val SRLI  = BitPat("b000000???????????101?????0010011")
   val SRLIW = BitPat("b0000000??????????101?????0011011")
-  val SRA = BitPat("b0100000??????????101?????0110011")
-  val SRAW = BitPat("b0100000??????????101?????0111011")
-  val SRAI = BitPat("b010000???????????101?????0010011")
+  val SRA   = BitPat("b0100000??????????101?????0110011")
+  val SRAW  = BitPat("b0100000??????????101?????0111011")
+  val SRAI  = BitPat("b010000???????????101?????0010011")
   val SRAIW = BitPat("b0100000??????????101?????0011011")
 
   // Arithmetic
-  val ADD = BitPat("b0000000??????????000?????0110011")
-  val ADDW = BitPat("b0000000??????????000?????0111011")
-  val ADDI = BitPat("b?????????????????000?????0010011")
+  val ADD   = BitPat("b0000000??????????000?????0110011")
+  val ADDW  = BitPat("b0000000??????????000?????0111011")
+  val ADDI  = BitPat("b?????????????????000?????0010011")
   val ADDIW = BitPat("b?????????????????000?????0011011")
-  val SUB = BitPat("b0100000??????????000?????0110011")
-  val SUBW = BitPat("b0100000??????????000?????0111011")
-  val LUI = BitPat("b?????????????????????????0110111")
+  val SUB   = BitPat("b0100000??????????000?????0110011")
+  val SUBW  = BitPat("b0100000??????????000?????0111011")
+  val LUI   = BitPat("b?????????????????????????0110111")
   val AUIPC = BitPat("b?????????????????????????0010111")
 
   // Logical
-  val XOR = BitPat("b0000000??????????100?????0110011")
+  val XOR  = BitPat("b0000000??????????100?????0110011")
   val XORI = BitPat("b?????????????????100?????0010011")
-  val OR = BitPat("b0000000??????????110?????0110011")
-  val ORI = BitPat("b?????????????????110?????0010011")
-  val AND = BitPat("b0000000??????????111?????0110011")
+  val OR   = BitPat("b0000000??????????110?????0110011")
+  val ORI  = BitPat("b?????????????????110?????0010011")
+  val AND  = BitPat("b0000000??????????111?????0110011")
   val ANDI = BitPat("b?????????????????111?????0010011")
   // Compare
-  val SLT = BitPat("b0000000??????????010?????0110011")
-  val SLTI = BitPat("b?????????????????010?????0010011")
-  val SLTU = BitPat("b0000000??????????011?????0110011")
+  val SLT   = BitPat("b0000000??????????010?????0110011")
+  val SLTI  = BitPat("b?????????????????010?????0010011")
+  val SLTU  = BitPat("b0000000??????????011?????0110011")
   val SLTIU = BitPat("b?????????????????011?????0010011")
   // Branches
-  val BEQ = BitPat("b?????????????????000?????1100011")
-  val BNE = BitPat("b?????????????????001?????1100011")
-  val BLT = BitPat("b?????????????????100?????1100011")
-  val BGE = BitPat("b?????????????????101?????1100011")
+  val BEQ  = BitPat("b?????????????????000?????1100011")
+  val BNE  = BitPat("b?????????????????001?????1100011")
+  val BLT  = BitPat("b?????????????????100?????1100011")
+  val BGE  = BitPat("b?????????????????101?????1100011")
   val BLTU = BitPat("b?????????????????110?????1100011")
   val BGEU = BitPat("b?????????????????111?????1100011")
   // Jump & Link
   val JALR = BitPat("b?????????????????000?????1100111")
-  val JAL = BitPat("b?????????????????????????1101111")
+  val JAL  = BitPat("b?????????????????????????1101111")
   // Synch
-  val FENCE = BitPat("b?????????????????000?????0001111")
+  val FENCE   = BitPat("b?????????????????000?????0001111")
   val FENCE_I = BitPat("b?????????????????001?????0001111")
   // ZiCSR
-  val CSRRW = BitPat("b?????????????????001?????1110011")
-  val CSRRS = BitPat("b?????????????????010?????1110011")
-  val CSRRC = BitPat("b?????????????????011?????1110011")
+  val CSRRW  = BitPat("b?????????????????001?????1110011")
+  val CSRRS  = BitPat("b?????????????????010?????1110011")
+  val CSRRC  = BitPat("b?????????????????011?????1110011")
   val CSRRWI = BitPat("b?????????????????101?????1110011")
   val CSRRSI = BitPat("b?????????????????110?????1110011")
   val CSRRCI = BitPat("b?????????????????111?????1110011")
-  // RVM（暂不需要）
-  val MUL = BitPat("b0000001??????????000?????0110011")
-  val MULW = BitPat("b0000001??????????000?????0111011")
-  val MULH = BitPat("b0000001??????????001?????0110011")
+  // M Extension
+  val MUL    = BitPat("b0000001??????????000?????0110011")
+  val MULW   = BitPat("b0000001??????????000?????0111011")
+  val MULH   = BitPat("b0000001??????????001?????0110011")
   val MULHSU = BitPat("b0000001??????????010?????0110011")
-  val MULHU = BitPat("b0000001??????????011?????0110011")
-  val DIV = BitPat("b0000001??????????100?????0110011")
-  val DIVW = BitPat("b0000001??????????100?????0111011")
-  val DIVU = BitPat("b0000001??????????101?????0110011")
-  val DIVUW = BitPat("b0000001??????????101?????0111011")
-  val REM = BitPat("b0000001??????????110?????0110011")
-  val REMW = BitPat("b0000001??????????110?????0111011")
-  val REMU = BitPat("b0000001??????????111?????0110011")
-  val REMUW = BitPat("b0000001??????????111?????0111011")
+  val MULHU  = BitPat("b0000001??????????011?????0110011")
+  val DIV    = BitPat("b0000001??????????100?????0110011")
+  val DIVW   = BitPat("b0000001??????????100?????0111011")
+  val DIVU   = BitPat("b0000001??????????101?????0110011")
+  val DIVUW  = BitPat("b0000001??????????101?????0111011")
+  val REM    = BitPat("b0000001??????????110?????0110011")
+  val REMW   = BitPat("b0000001??????????110?????0111011")
+  val REMU   = BitPat("b0000001??????????111?????0110011")
+  val REMUW  = BitPat("b0000001??????????111?????0111011")
   // SYSTEM Instruction
-  val ECALL = BitPat("b00000000000000000000000001110011")
+  val ECALL  = BitPat("b00000000000000000000000001110011")
   val EBREAK = BitPat("b00000000000100000000000001110011")
   // TRAP RETURN INSTURCTIONS
   val URET = BitPat("b00000000001000000000000001110011")
@@ -100,7 +100,20 @@ object Instructions {
   val SFENCE_VMA = BitPat("b0001001??????????000000001110011")
   // INTERRUPT MANAGEMENT INSTRUCTION
   val WFI = BitPat("b00010000010100000000000001110011")
-
+  // A Extension
+  val LR_D    = BitPat("b00010_??_00000_?????_011_?????_0101111")
+  val SC_D    = BitPat("b00011_??_?????_?????_011_?????_0101111")
+  val LR_W    = BitPat("b00010_??_00000_?????_010_?????_0101111")
+  val SC_W    = BitPat("b00011_??_?????_?????_010_?????_0101111")
+  val AMOSWAP = BitPat("b00001_??_?????_?????_01?_?????_0101111")
+  val AMOADD  = BitPat("b00000_??_?????_?????_01?_?????_0101111")
+  val AMOXOR  = BitPat("b00100_??_?????_?????_01?_?????_0101111")
+  val AMOAND  = BitPat("b01100_??_?????_?????_01?_?????_0101111")
+  val AMOOR   = BitPat("b01000_??_?????_?????_01?_?????_0101111")
+  val AMOMIN  = BitPat("b10000_??_?????_?????_01?_?????_0101111")
+  val AMOMAX  = BitPat("b10100_??_?????_?????_01?_?????_0101111")
+  val AMOMINU = BitPat("b11000_??_?????_?????_01?_?????_0101111")
+  val AMOMAXU = BitPat("b11100_??_?????_?????_01?_?????_0101111")
 
 }
 

diff --git a/src/main/scala/core/mem.scala b/src/main/scala/core/mem.scala
@@ -132,6 +132,7 @@ class MEM extends Module {
   // TODO Ends
   val isMMIO = MMIO.inMMIORange(io.exe2Mem.aluResult)
   val memRdata = Mux(readClint, io.toclint.rdata, io.mem2dmem.memRdata)
+  val accessVAddr = io.exe2Mem.aluResult // TODO
   val address = io.exe2Mem.aluResult - 0x80000000L.U
   val signExt = io.exe2Mem.MemType === SZ_B || io.exe2Mem.MemType === SZ_H || io.exe2Mem.MemType === SZ_W
   val memRead = io.exe2Mem.isMemOp & io.exe2Mem.MemOp === MEM_READ & !isMMIO & !io.exe2Mem.exceInfo.valid
@@ -195,6 +196,26 @@ class MEM extends Module {
   }
   // MMIO Flag
   BoringUtils.addSource(RegNext(io.exe2Mem.isMemOp & isMMIO), "difftestIsMMIO")
+
+  // LR/SC Handler
+  val isLR = WireInit(false.B)
+  val isSC = WireInit(false.B)
+  val reservationSet = Reg(UInt(64.W))
+  val reservationValid = RegInit(false.B)
+  when(isLR) {  // Update the reservation set
+    reservationValid := true.B
+    reservationSet := accessVAddr
+  }.elsewhen(isSC){
+    reservationValid := false.B
+  }
+  // LSU 
+  // IDLE -> ReqPADDR -> OP -> IDLE
+  val scWillSuccess = reservationValid && reservationSet === accessVAddr
+  // If is SC and SC will fail, write back the failing code 
+  val sIDLE :: sWAIT_RD :: sWAIT_WR :: Nil = Enum(3)
+  // IDLE -> read_req -> transfer to WAIT_RD 
+  // WAIT_RD -> rvalid -> transfer to IDLE  / isAMO -> transfer to WAIT_WR
+  // WVALID -> valid -> 
 }
 
 object MEM extends App {