chore: Update hugr

Cargo.toml

@@ -22,9 +22,9 @@ thiserror = "1.0.28"
 serde = { version = "1.0", features = ["derive"] }
 serde_json = "1.0"
 downcast-rs = "1.2.0"
-portgraph = "0.7.0"
+portgraph = "0.7.1"
 priority-queue = "1.3.0"
-quantinuum-hugr = { git = "https://github.com/CQCL-DEV/hugr", tag = "v0.0.0-alpha.4" }
+quantinuum-hugr = { git = "https://github.com/CQCL-DEV/hugr", tag = "v0.0.0-alpha.5" }
 smol_str = "0.2.0"
 typetag = "0.2.8"
 itertools = "0.11.0"

pyrs/Cargo.toml

@@ -11,8 +11,8 @@ crate-type = ["cdylib"]
 [dependencies]
 pyo3 = { version = "0.19", features = ["extension-module"] }
 tket2 = { path = "../", features = ["pyo3"] }
-portgraph = { version = "0.7.0", features = ["pyo3"] }
+portgraph = { version = "0.7.1", features = ["pyo3"] }
 serde = { version = "1.0", features = ["derive"] }
 serde_json = "1.0"
 tket-json-rs = { git = "https://github.com/CQCL/tket-json-rs", features = ["pyo3"] }
-quantinuum-hugr = { git = "https://github.com/CQCL-DEV/hugr", tag = "v0.0.0-alpha.4" }
+quantinuum-hugr = { git = "https://github.com/CQCL-DEV/hugr", tag = "v0.0.0-alpha.5" }

src/circuit.rs

@@ -13,13 +13,14 @@ pub mod command;
 
 use crate::utils::QB;
 
-use self::command::{Command, CommandIterator, Unit};
+use self::command::{Command, CommandIterator};
 
+use hugr::hugr::CircuitUnit;
 use hugr::ops::OpTrait;
 
 pub use hugr::hugr::region::Region;
 pub use hugr::ops::OpType;
-pub use hugr::types::{ClassicType, EdgeKind, LinearType, Signature, SimpleType, TypeRow};
+pub use hugr::types::{ClassicType, EdgeKind, Signature, SimpleType, TypeRow};
 pub use hugr::{Node, Port, Wire};
 use petgraph::visit::{GraphBase, IntoNeighborsDirected, IntoNodeIdentifiers};
 
@@ -41,11 +42,11 @@ pub trait Circuit<'circ> {
     fn name(&self) -> Option<&str>;
 
     /// Get the linear inputs of the circuit and their types.
-    fn units(&self) -> Vec<(Unit, SimpleType)>;
+    fn units(&self) -> Vec<(CircuitUnit, SimpleType)>;
 
     /// Returns the ports corresponding to qubits inputs to the circuit.
     #[inline]
-    fn qubits(&self) -> Vec<Unit> {
+    fn qubits(&self) -> Vec<CircuitUnit> {
         self.units()
             .iter()
             .filter(|(_, typ)| typ == &QB)
@@ -78,14 +79,14 @@ where
     }
 
     #[inline]
-    fn units(&self) -> Vec<(Unit, SimpleType)> {
+    fn units(&self) -> Vec<(CircuitUnit, SimpleType)> {
         let root = self.root();
         let optype = self.get_optype(root);
         optype
             .signature()
             .input_df_types()
             .iter()
-            .filter(|typ| typ.is_linear())
+            .filter(|typ| !typ.is_classical())
             .enumerate()
             .map(|(i, typ)| (i.into(), typ.clone()))
             .collect()

src/circuit/command.rs

@@ -7,38 +7,14 @@ use std::iter::FusedIterator;
 
 use hugr::hugr::region::Region;
 use hugr::ops::OpTrait;
-pub use hugr::ops::OpType;
-pub use hugr::types::{ClassicType, EdgeKind, LinearType, Signature, SimpleType, TypeRow};
-pub use hugr::{Node, Port, Wire};
 use petgraph::visit::{GraphBase, IntoNeighborsDirected, IntoNodeIdentifiers};
 
 use super::Circuit;
 
-/// Descriptor of a wire in a [`Circuit`]. If it is a qubit or linear bit
-/// originating from the circuit's input, it is described by an index.
-/// Otherwise, it is described by an internal [`Wire`].
-//
-// TODO Better name?
-// TODO Merge this with CircuitBuilder::AppendWire?
-#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub enum Unit {
-    /// Arbitrary wire.
-    W(Wire),
-    /// Index of a linear element in the [`Circuit`]'s input vector.
-    Linear(usize),
-}
-
-impl From<usize> for Unit {
-    fn from(value: usize) -> Self {
-        Unit::Linear(value)
-    }
-}
-
-impl From<Wire> for Unit {
-    fn from(value: Wire) -> Self {
-        Unit::W(value)
-    }
-}
+pub use hugr::hugr::CircuitUnit;
+pub use hugr::ops::OpType;
+pub use hugr::types::{ClassicType, EdgeKind, Signature, SimpleType, TypeRow};
+pub use hugr::{Node, Port, Wire};
 
 /// An operation applied to specific wires.
 pub struct Command<'circ> {
@@ -47,9 +23,9 @@ pub struct Command<'circ> {
     /// The operation node.
     pub node: Node,
     /// The input units to the operation.
-    pub inputs: Vec<Unit>,
+    pub inputs: Vec<CircuitUnit>,
     /// The output units to the operation.
-    pub outputs: Vec<Unit>,
+    pub outputs: Vec<CircuitUnit>,
 }
 
 /// An iterator over the commands of a circuit.
@@ -61,7 +37,7 @@ pub struct CommandIterator<'circ, Circ> {
     nodes: Vec<Node>,
     /// Current element in `nodes`
     current: usize,
-    /// Last wires for each linear `Unit`
+    /// Last wires for each linear `CircuitUnit`
     wire_unit: HashMap<Wire, usize>,
 }
 
@@ -100,9 +76,9 @@ where
                         if let Some(new_port) = self.circ.follow_linear_port(node, port) {
                             self.wire_unit.insert(Wire::new(node, new_port), unit);
                         }
-                        Some(Unit::Linear(unit))
+                        Some(CircuitUnit::Linear(unit))
                     }
-                    None => Some(Unit::W(wire)),
+                    None => Some(CircuitUnit::Wire(wire)),
                 }
             })
             .collect();
@@ -112,8 +88,8 @@ where
             .map(|port| {
                 let wire = Wire::new(node, port);
                 match self.wire_unit.get(&wire) {
-                    Some(&unit) => Unit::Linear(unit),
-                    None => Unit::W(wire),
+                    Some(&unit) => CircuitUnit::Linear(unit),
+                    None => CircuitUnit::Wire(wire),
                 }
             })
             .collect();

src/json/decoder.rs

@@ -5,7 +5,8 @@ use std::collections::HashMap;
 use std::hash::{Hash, Hasher};
 use std::mem;
 
-use hugr::builder::{AppendWire, CircuitBuilder, Container, DFGBuilder, Dataflow, DataflowHugr};
+use hugr::builder::{CircuitBuilder, Container, DFGBuilder, Dataflow, DataflowHugr};
+use hugr::hugr::CircuitUnit;
 use hugr::ops::ConstValue;
 use hugr::types::Signature;
 use hugr::{Hugr, Wire};
@@ -98,8 +99,8 @@ impl JsonDecoder {
 
         let append_wires = args
             .into_iter()
-            .map(AppendWire::I)
-            .chain(param_wires.into_iter().map(AppendWire::W));
+            .map(CircuitUnit::Linear)
+            .chain(param_wires.into_iter().map(CircuitUnit::Wire));
 
         self.with_circ_builder(|circ| {
             circ.append_and_consume(&op, append_wires).unwrap();

src/passes/taso/qtz_circuit.rs

@@ -7,7 +7,7 @@ use hugr::builder::{DFGBuilder, Dataflow, DataflowHugr};
 //     operation::{Op, WireType},
 // };
 use hugr::ops::{LeafOp, OpType as Op};
-use hugr::types::{ClassicType, LinearType, SimpleType};
+use hugr::types::{ClassicType, SimpleType};
 use hugr::Hugr as Circuit;
 use serde::{Deserialize, Serialize};
 
@@ -50,7 +50,7 @@ fn map_op(opstr: &str) -> Op {
 
 fn map_wt(wirestr: &str) -> (SimpleType, usize) {
     let wt = if wirestr.starts_with('Q') {
-        LinearType::Qubit.into()
+        SimpleType::Qubit
     } else if wirestr.starts_with('P') {
         ClassicType::F64.into()
     } else {
@@ -62,7 +62,7 @@ fn map_wt(wirestr: &str) -> (SimpleType, usize) {
 // TODO change to TryFrom
 impl From<RepCircData> for Circuit {
     fn from(RepCircData { circ: rc, meta }: RepCircData) -> Self {
-        let qb_types: Vec<SimpleType> = vec![LinearType::Qubit.into(); meta.n_qb];
+        let qb_types: Vec<SimpleType> = vec![SimpleType::Qubit; meta.n_qb];
         let param_types: Vec<SimpleType> = vec![ClassicType::F64.into(); meta.n_input_param];
         let mut circ = DFGBuilder::new([param_types, qb_types.clone()].concat(), qb_types).unwrap();
 
@@ -86,7 +86,7 @@ impl From<RepCircData> for Circuit {
                 .map(|is| {
                     let (wt, idx) = map_wt(&is);
                     match wt {
-                        SimpleType::Linear(LinearType::Qubit) => qubit_wires[idx],
+                        SimpleType::Qubit => qubit_wires[idx],
                         SimpleType::Classic(ClassicType::F64) => *param_wires[idx].take().unwrap(),
                         _ => panic!("unexpected wire type."),
                     }
@@ -96,11 +96,7 @@ impl From<RepCircData> for Circuit {
 
             for (os, wire) in outputs.into_iter().zip(output_wires) {
                 let (wt, idx) = map_wt(&os);
-                assert_eq!(
-                    wt,
-                    SimpleType::Linear(LinearType::Qubit),
-                    "only qubits expected as output"
-                );
+                assert_eq!(wt, SimpleType::Qubit, "only qubits expected as output");
 
                 qubit_wires[idx] = wire;
             }
@@ -138,6 +134,8 @@ pub(super) fn load_ecc_set(path: &str) -> HashMap<String, Vec<Circuit>> {
 mod tests {
     // use crate::validate::check_soundness;
 
+    use hugr::HugrView;
+
     use super::*;
     fn load_representative_set(path: &str) -> HashMap<String, Circuit> {
         let jsons = std::fs::read_to_string(path).unwrap();

src/utils.rs

@@ -1,8 +1,8 @@
 //! Utility functions for the library.
 
-use hugr::types::{ClassicType, LinearType, SimpleType};
+use hugr::types::{ClassicType, SimpleType};
 
-pub(crate) const QB: SimpleType = SimpleType::Linear(LinearType::Qubit);
+pub(crate) const QB: SimpleType = SimpleType::Qubit;
 pub(crate) const BIT: SimpleType = SimpleType::Classic(ClassicType::Int(1));
 pub(crate) const F64: SimpleType = SimpleType::Classic(ClassicType::F64);