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Merge tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/…
…kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: - support for interrupt virtualization in the AMD IOMMU driver. These patches were shared with the KVM tree and are already merged through that tree. - generic DT-binding support for the ARM-SMMU driver. With this the driver now makes use of the generic DMA-API code. This also required some changes outside of the IOMMU code, but these are acked by the respective maintainers. - more cleanups and fixes all over the place. * tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (40 commits) iommu/amd: No need to wait iommu completion if no dte irq entry change iommu/amd: Free domain id when free a domain of struct dma_ops_domain iommu/amd: Use standard bitmap operation to set bitmap iommu/amd: Clean up the cmpxchg64 invocation iommu/io-pgtable-arm: Check for v7s-incapable systems iommu/dma: Avoid PCI host bridge windows iommu/dma: Add support for mapping MSIs iommu/arm-smmu: Set domain geometry iommu/arm-smmu: Wire up generic configuration support Docs: dt: document ARM SMMU generic binding usage iommu/arm-smmu: Convert to iommu_fwspec iommu/arm-smmu: Intelligent SMR allocation iommu/arm-smmu: Add a stream map entry iterator iommu/arm-smmu: Streamline SMMU data lookups iommu/arm-smmu: Refactor mmu-masters handling iommu/arm-smmu: Keep track of S2CR state iommu/arm-smmu: Consolidate stream map entry state iommu/arm-smmu: Handle stream IDs more dynamically iommu/arm-smmu: Set PRIVCFG in stage 1 STEs iommu/arm-smmu: Support non-PCI devices with SMMUv3 ...
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This document describes the generic device tree binding for describing the | ||
relationship between PCI(e) devices and IOMMU(s). | ||
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Each PCI(e) device under a root complex is uniquely identified by its Requester | ||
ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and | ||
Function number. | ||
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For the purpose of this document, when treated as a numeric value, a RID is | ||
formatted such that: | ||
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* Bits [15:8] are the Bus number. | ||
* Bits [7:3] are the Device number. | ||
* Bits [2:0] are the Function number. | ||
* Any other bits required for padding must be zero. | ||
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IOMMUs may distinguish PCI devices through sideband data derived from the | ||
Requester ID. While a given PCI device can only master through one IOMMU, a | ||
root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per | ||
bus). | ||
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The generic 'iommus' property is insufficient to describe this relationship, | ||
and a mechanism is required to map from a PCI device to its IOMMU and sideband | ||
data. | ||
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For generic IOMMU bindings, see | ||
Documentation/devicetree/bindings/iommu/iommu.txt. | ||
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PCI root complex | ||
================ | ||
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Optional properties | ||
------------------- | ||
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- iommu-map: Maps a Requester ID to an IOMMU and associated iommu-specifier | ||
data. | ||
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The property is an arbitrary number of tuples of | ||
(rid-base,iommu,iommu-base,length). | ||
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Any RID r in the interval [rid-base, rid-base + length) is associated with | ||
the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base). | ||
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- iommu-map-mask: A mask to be applied to each Requester ID prior to being | ||
mapped to an iommu-specifier per the iommu-map property. | ||
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Example (1) | ||
=========== | ||
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/ { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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iommu: iommu@a { | ||
reg = <0xa 0x1>; | ||
compatible = "vendor,some-iommu"; | ||
#iommu-cells = <1>; | ||
}; | ||
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pci: pci@f { | ||
reg = <0xf 0x1>; | ||
compatible = "vendor,pcie-root-complex"; | ||
device_type = "pci"; | ||
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/* | ||
* The sideband data provided to the IOMMU is the RID, | ||
* identity-mapped. | ||
*/ | ||
iommu-map = <0x0 &iommu 0x0 0x10000>; | ||
}; | ||
}; | ||
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Example (2) | ||
=========== | ||
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/ { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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iommu: iommu@a { | ||
reg = <0xa 0x1>; | ||
compatible = "vendor,some-iommu"; | ||
#iommu-cells = <1>; | ||
}; | ||
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pci: pci@f { | ||
reg = <0xf 0x1>; | ||
compatible = "vendor,pcie-root-complex"; | ||
device_type = "pci"; | ||
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/* | ||
* The sideband data provided to the IOMMU is the RID with the | ||
* function bits masked out. | ||
*/ | ||
iommu-map = <0x0 &iommu 0x0 0x10000>; | ||
iommu-map-mask = <0xfff8>; | ||
}; | ||
}; | ||
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Example (3) | ||
=========== | ||
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/ { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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iommu: iommu@a { | ||
reg = <0xa 0x1>; | ||
compatible = "vendor,some-iommu"; | ||
#iommu-cells = <1>; | ||
}; | ||
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pci: pci@f { | ||
reg = <0xf 0x1>; | ||
compatible = "vendor,pcie-root-complex"; | ||
device_type = "pci"; | ||
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/* | ||
* The sideband data provided to the IOMMU is the RID, | ||
* but the high bits of the bus number are flipped. | ||
*/ | ||
iommu-map = <0x0000 &iommu 0x8000 0x8000>, | ||
<0x8000 &iommu 0x0000 0x8000>; | ||
}; | ||
}; | ||
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Example (4) | ||
=========== | ||
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/ { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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iommu_a: iommu@a { | ||
reg = <0xa 0x1>; | ||
compatible = "vendor,some-iommu"; | ||
#iommu-cells = <1>; | ||
}; | ||
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iommu_b: iommu@b { | ||
reg = <0xb 0x1>; | ||
compatible = "vendor,some-iommu"; | ||
#iommu-cells = <1>; | ||
}; | ||
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iommu_c: iommu@c { | ||
reg = <0xc 0x1>; | ||
compatible = "vendor,some-iommu"; | ||
#iommu-cells = <1>; | ||
}; | ||
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pci: pci@f { | ||
reg = <0xf 0x1>; | ||
compatible = "vendor,pcie-root-complex"; | ||
device_type = "pci"; | ||
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/* | ||
* Devices with bus number 0-127 are mastered via IOMMU | ||
* a, with sideband data being RID[14:0]. | ||
* Devices with bus number 128-255 are mastered via | ||
* IOMMU b, with sideband data being RID[14:0]. | ||
* No devices master via IOMMU c. | ||
*/ | ||
iommu-map = <0x0000 &iommu_a 0x0000 0x8000>, | ||
<0x8000 &iommu_b 0x0000 0x8000>; | ||
}; | ||
}; |
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