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fwrisc
fwrisc PublicForked from Featherweight-IP/fwrisc
Featherweight RISC-V implementation
SystemVerilog
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AHB-LITE-Verification
AHB-LITE-Verification PublicVerification of AHB-lite bus interface
SystemVerilog
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ara
ara PublicForked from pulp-platform/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
C
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cva6
cva6 PublicForked from pulp-platform/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
C++
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