Fix SpinalHDL#106 SpinalHDL#103

implement tsr, tw, tvm (tw as dummy)
KinzaQamar · May 30, 2024 · ed2df82 · ed2df82
1 parent e5f3abb
commit ed2df82
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Showing 3 changed files with 22 additions and 8 deletions.
diff --git a/src/main/scala/naxriscv/execute/EnvCallPlugin.scala b/src/main/scala/naxriscv/execute/EnvCallPlugin.scala
@@ -89,25 +89,32 @@ class EnvCallPlugin(val euId : String)(var rescheduleAt : Int = 0) extends Plugi
     setup.reschedule.cause.assignDontCare()
 
     val xretPriv = Frontend.MICRO_OP(29 downto 28).asUInt
+    val trap = False
     when(XRET){
       setup.reschedule.cause            := CAUSE_XRET //the reschedule cause isn't the final value which will end up into XCAUSE csr
       setup.reschedule.tval(1 downto 0) := xretPriv.asBits
-      when(xretPriv > priv.getPrivilege()){
-        setup.reschedule.cause      := CSR.MCAUSE_ENUM.ILLEGAL_INSTRUCTION
-        setup.reschedule.reason     := ScheduleReason.TRAP
-        setup.reschedule.skipCommit := True
-      }
+      trap setWhen (xretPriv > priv.getPrivilege())
+      if(priv.p.withSupervisor) trap setWhen (priv.logic.machine.mstatus.tsr && priv.getPrivilege() === 1 && xretPriv === 1)
     }
     when(EBREAK){
       setup.reschedule.cause      := CSR.MCAUSE_ENUM.BREAKPOINT
     }
     when(ECALL){
       setup.reschedule.cause      := CSR.MCAUSE_ENUM.ECALL_MACHINE //the reschedule cause isn't the final value which will end up into XCAUSE csr
     }
-
     when(FENCE_I || FENCE_VMA || FLUSH_DATA){
       setup.reschedule.cause      := CAUSE_FLUSH
     }
+    if(priv.p.withSupervisor) when(FENCE_VMA){
+      trap setWhen(priv.getPrivilege() === 1 && priv.logic.machine.mstatus.tvm)
+      trap setWhen(priv.getPrivilege() === 0)
+    }
+
+    when(trap){
+      setup.reschedule.cause := CSR.MCAUSE_ENUM.ILLEGAL_INSTRUCTION
+      setup.reschedule.reason := ScheduleReason.TRAP
+      setup.reschedule.skipCommit := True
+    }
 
     //Handle FENCE.I and FENCE.VMA
     val flushes = new StateMachine{

diff --git a/src/main/scala/naxriscv/misc/MmuPlugin.scala b/src/main/scala/naxriscv/misc/MmuPlugin.scala
@@ -201,8 +201,12 @@ class MmuPlugin(var spec : MmuSpec,
 //    csr.readWriteRam(CSR.SATP) not suported by writeCancel
 
     csr.onDecode(CSR.SATP){
-      csr.onDecodeFlushPipeline()
-      setup.invalidatePort.cmd.valid := True
+      when(priv.logic.machine.mstatus.tvm && priv.getPrivilege() === 1){
+        csr.onDecodeTrap()
+      } otherwise {
+        csr.onDecodeFlushPipeline()
+        setup.invalidatePort.cmd.valid := True
+      }
     }
 
     ram.allocationLock.release()

diff --git a/src/main/scala/naxriscv/misc/PrivilegedPlugin.scala b/src/main/scala/naxriscv/misc/PrivilegedPlugin.scala
@@ -391,6 +391,8 @@ class PrivilegedPlugin(var p : PrivilegedConfig) extends Plugin with PrivilegedS
         val sd = False
         if(RVF) setup.isFpuEnabled setWhen(fs =/= 0)
         if(withFs) sd setWhen(fs === 3)
+
+        val tsr, tw, tvm = p.withSupervisor generate RegInit(False)
       }
       val mip = new Area{
         val meip = RegNext(io.int.machine.external) init(False)
@@ -432,6 +434,7 @@ class PrivilegedPlugin(var p : PrivilegedConfig) extends Plugin with PrivilegedS
       csr.read     (CSR.MSTATUS, XLEN-1 -> mstatus.sd)
       csr.read     (CSR.MIP, 11 -> mip.meip, 7 -> mip.mtip, 3 -> mip.msip)
       csr.readWrite(CSR.MIE, 11 -> mie.meie, 7 -> mie.mtie, 3 -> mie.msie)
+      if(p.withSupervisor) csr.readWrite(CSR.MSTATUS, 22 -> mstatus.tsr, 21 -> mstatus.tw, 20 -> mstatus.tvm)
 
 
       if(withFs) csr.readWrite(CSR.MSTATUS, 13 -> mstatus.fs)