Update to Scala 2.12 and fix litex mbus offset

build.sbt

@@ -8,13 +8,14 @@ lazy val root = (project in file(".")).
   settings(
     inThisBuild(List(
       organization := "com.github.spinalhdl",
-      scalaVersion := "2.11.12",
+      scalaVersion := "2.12.18",
       version      := "2.0.0"
     )),
-    scalacOptions +=  s"-Xplugin:${new File(baseDirectory.value + s"/ext/SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}",
+    scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/ext/SpinalHDL/idslplugin/target/scala-2.12/spinalhdl-idsl-plugin_2.12-$spinalVersion.jar")}",
     scalacOptions += s"-Xplugin-require:idsl-plugin",
+    scalacOptions += "-language:reflectiveCalls",
     libraryDependencies ++= Seq(
-      "org.scalatest" %% "scalatest" % "3.2.5",
+      "org.scalatest" %% "scalatest" % "3.2.17",
       "org.yaml" % "snakeyaml" % "1.8",
       "net.fornwall" % "jelf" % "0.7.0"
     ),

src/main/scala/naxriscv/execute/BranchPlugin.scala

@@ -45,21 +45,22 @@ class BranchPlugin(val euId : String,
   override def euWritebackAt = writebackAt
   override def euCompletionAt = branchAt max writebackAt
 
-  override val setup = create early new Setup{
+  override val setup = create early new BranchSetup
+  class BranchSetup extends Setup {
     getService[RobService].retain()
     val sk = SrcKeys
 
-    add(Rvi.JAL , List(                                    ), List(BRANCH_CTRL -> BranchCtrlEnum.JAL))
-    add(Rvi.JALR, List(              sk.SRC1.RF            ), List(BRANCH_CTRL -> BranchCtrlEnum.JALR))
-    add(Rvi.BEQ , List(              sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
-    add(Rvi.BNE , List(              sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
-    add(Rvi.BLT , List(sk.Op.LESS  , sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
-    add(Rvi.BGE , List(sk.Op.LESS  , sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
+    add(Rvi.JAL, List(), List(BRANCH_CTRL -> BranchCtrlEnum.JAL))
+    add(Rvi.JALR, List(sk.SRC1.RF), List(BRANCH_CTRL -> BranchCtrlEnum.JALR))
+    add(Rvi.BEQ, List(sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
+    add(Rvi.BNE, List(sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
+    add(Rvi.BLT, List(sk.Op.LESS, sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
+    add(Rvi.BGE, List(sk.Op.LESS, sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
     add(Rvi.BLTU, List(sk.Op.LESS_U, sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
     add(Rvi.BGEU, List(sk.Op.LESS_U, sk.SRC1.RF, sk.SRC2.RF), List(BRANCH_CTRL -> BranchCtrlEnum.B))
 
     val withBranchContext = isServiceAvailable[BranchContextPlugin]
-    if(withBranchContext){
+    if (withBranchContext) {
       eu.addRobStageable(getService[BranchContextPlugin].keys.BRANCH_ID)
     }
     val reschedule = getService[CommitService].newSchedulePort(canJump = true, canTrap = !Global.RVC)

src/main/scala/naxriscv/execute/CsrAccessPlugin.scala

@@ -12,7 +12,7 @@ import spinal.lib._
 import naxriscv.utilities._
 import spinal.lib.pipeline._
 import naxriscv.Frontend._
-import naxriscv.Global._
+import naxriscv.Global.{XLEN, _}
 import naxriscv.frontend.DispatchPlugin
 import naxriscv.misc.CommitPlugin
 import spinal.lib.fsm.{State, StateMachine}
@@ -61,7 +61,8 @@ class CsrAccessPlugin(val euId: String)(var writebackAt: Int) extends ExecutionU
   override def onReadToWriteBits = setup.onReadToWriteBits
   override def onWriteFlushPipeline() = setup.onWriteFlushPipeline := True
 
-  val setup = create early new Setup{
+  val setup = create early new CsrSetup
+  class CsrSetup extends Setup {
     val dispatch = getService[DispatchPlugin]
     getServiceOption[CsrRamService] match {
       case Some(x) => x.portLock.retain()
@@ -71,29 +72,29 @@ class CsrAccessPlugin(val euId: String)(var writebackAt: Int) extends ExecutionU
 
     val onDecodeTrap = False
     val onDecodeFlushPipeline = False
-    val onDecodeRead  = Bool()
+    val onDecodeRead = Bool()
     val onDecodeWrite = Bool()
     val onDecodeAddress = UInt(12 bits)
 
-    val onReadHalt  = False
+    val onReadHalt = False
     val onWriteHalt = False
 
     val onReadToWriteBits = Bits(XLEN bits)
     val onWriteBits = Bits(XLEN bits)
     val onWriteAddress = UInt(12 bits)
     val onWriteFlushPipeline = False
-    val onReadAddress  = UInt(12 bits)
+    val onReadAddress = UInt(12 bits)
     val onReadMovingOff = Bool()
     val onWriteMovingOff = Bool()
 
-    add(Rvi.CSRRW , Nil, DecodeList(CSR_IMM -> False, CSR_MASK -> False))
-    add(Rvi.CSRRS , Nil, DecodeList(CSR_IMM -> False, CSR_MASK -> True , CSR_CLEAR -> False))
-    add(Rvi.CSRRC , Nil, DecodeList(CSR_IMM -> False, CSR_MASK -> True , CSR_CLEAR -> True))
-    add(Rvi.CSRRWI, Nil, DecodeList(CSR_IMM -> True , CSR_MASK -> False))
-    add(Rvi.CSRRSI, Nil, DecodeList(CSR_IMM -> True , CSR_MASK -> True , CSR_CLEAR -> False))
-    add(Rvi.CSRRCI, Nil, DecodeList(CSR_IMM -> True , CSR_MASK -> True , CSR_CLEAR -> True))
+    add(Rvi.CSRRW, Nil, DecodeList(CSR_IMM -> False, CSR_MASK -> False))
+    add(Rvi.CSRRS, Nil, DecodeList(CSR_IMM -> False, CSR_MASK -> True, CSR_CLEAR -> False))
+    add(Rvi.CSRRC, Nil, DecodeList(CSR_IMM -> False, CSR_MASK -> True, CSR_CLEAR -> True))
+    add(Rvi.CSRRWI, Nil, DecodeList(CSR_IMM -> True, CSR_MASK -> False))
+    add(Rvi.CSRRSI, Nil, DecodeList(CSR_IMM -> True, CSR_MASK -> True, CSR_CLEAR -> False))
+    add(Rvi.CSRRCI, Nil, DecodeList(CSR_IMM -> True, CSR_MASK -> True, CSR_CLEAR -> True))
 
-    for(op <- List(Rvi.CSRRW, Rvi.CSRRS, Rvi.CSRRC, Rvi.CSRRWI, Rvi.CSRRSI, Rvi.CSRRCI)){
+    for (op <- List(Rvi.CSRRW, Rvi.CSRRS, Rvi.CSRRC, Rvi.CSRRWI, Rvi.CSRRSI, Rvi.CSRRCI)) {
       dispatch.fenceYounger(op)
       dispatch.fenceOlder(op)
     }
@@ -102,7 +103,8 @@ class CsrAccessPlugin(val euId: String)(var writebackAt: Int) extends ExecutionU
     val trap = commit.newSchedulePort(canTrap = true, canJump = false)
   }
 
-  val logic = create late new Logic{
+  val logic = create late new CsrLogic
+  class CsrLogic extends Logic{
     val ram = getServiceOption[CsrRamService] match {
       case Some(x) => x
       case None => null
@@ -380,6 +382,7 @@ class CsrAccessPlugin(val euId: String)(var writebackAt: Int) extends ExecutionU
 
     val whitebox = new AreaRoot {
       import writebackLogic.stage._
+
       val csrAccess = Verilator.public(Flow(new Bundle {
         val robId = ROB.ID()
         val address = UInt(12 bits)

src/main/scala/naxriscv/platform/TilelinkNaxRiscvFiber.scala

@@ -31,29 +31,9 @@ import java.io.{BufferedWriter, File, FileWriter}
 import java.nio.file.Files
 import scala.collection.mutable.ArrayBuffer
 
-
-
-class TilelinkNaxRiscvFiber() extends Area with RiscvHart{
-  val iBus = Node.master()
-  val dBus = Node.master()
-  val pBus = Node.master()
-  val buses = List(iBus, dBus, pBus)
-  val plugins = Handle[Seq[Plugin]]
-
-  val icfs = ArrayBuffer[InterruptCtrlFiber]()
-  def bind(icf : InterruptCtrlFiber): Unit = {
-    icf.retain()
-    icfs += icf
-  }
-
-  val clint = Handle[TilelinkClintFiber]
-  def bind(clint : TilelinkClintFiber): Unit = {
-    clint.lock.retain()
-    this.clint load clint
-  }
-
-  def setCoherentConfig(hartId : Int, asic : Boolean = false, xlen : Int = 32) : this.type = {
-    plugins load Config.plugins(
+object TilelinkNaxRiscvFiber{
+  def getCoherentConfig(hartId: Int, asic: Boolean = false, xlen: Int = 32) = {
+    Config.plugins(
       withCoherency = true,
       withRdTime = false,
       aluCount = 2,
@@ -63,15 +43,31 @@ class TilelinkNaxRiscvFiber() extends Area with RiscvHart{
       asic = asic,
       xlen = xlen
     )
-    this
   }
-  def setPlugins(p : Seq[Plugin]) : this.type = {
-    plugins.load(p)
-    this
+}
+
+class TilelinkNaxRiscvFiber(val plugins : Seq[Plugin]) extends Area with RiscvHart{
+  val iBus = Node.master()
+  val dBus = Node.master()
+  val pBus = Node.master()
+  val buses = List(iBus, dBus, pBus)
+
+  def bind(icf : InterruptCtrlFiber): Unit = iBus.clockDomain{
+    val intIdPerHart = 1 + privPlugin.p.withSupervisor.toInt
+    mei << icf.createInterruptMaster(privPlugin.p.hartId*intIdPerHart)
+    if(sei != null) sei << icf.createInterruptMaster(privPlugin.p.hartId * intIdPerHart + 1)
   }
 
+  val clint = Handle[TilelinkClintFiber]
+  def bind(clint : TilelinkClintFiber): Unit = iBus.clockDomain{
+    this.clint load clint
+    val clintPort = clint.createPort(privPlugin.p.hartId).setCompositeName(this, "clintPort")
+    mti << clintPort.mti
+    msi << clintPort.msi
+    clintPort.stoptime := False
+  }
 
-  def privPlugin : PrivilegedPlugin = thread.core.framework.getService[PrivilegedPlugin]
+  def privPlugin : PrivilegedPlugin = plugins.collectFirst {case e : PrivilegedPlugin => e}.get
   override def getXlen() = thread.core.framework.getService[DecoderPlugin].xlen
   override def getFlen() = thread.core.framework.getServiceOption[FpuSettingPlugin] match {
     case Some(x) => x.rvd.toInt*64 max x.rvf.toInt*32
@@ -84,31 +80,14 @@ class TilelinkNaxRiscvFiber() extends Area with RiscvHart{
   override def getIntSupervisorExternal() = privPlugin.io.int.supervisor.external
   override def getDebugBus(): DebugHartBus = privPlugin.setup.debugBus
 
+  val mei = InterruptNode.slave()
+  val sei = privPlugin.p.withSupervisor generate InterruptNode.slave()
+  val mti, msi = InterruptNode.slave()
   val thread = Fiber build new Area{
     val l = ArrayBuffer[Plugin]()
     l ++= plugins
 
     val privPlugin = plugins.collectFirst{case p : PrivilegedPlugin => p }.get
-    val intIdPerHart = 1+privPlugin.p.withSupervisor.toInt
-    val mei = new Area{
-      val node = InterruptNode.slave()
-      val drivers = icfs.map(_.createInterruptMaster(privPlugin.p.hartId*intIdPerHart))
-      drivers.foreach(node << _)
-    }
-
-    val sei = privPlugin.p.withSupervisor generate new Area{
-      val node = InterruptNode.slave()
-      val drivers = icfs.map(_.createInterruptMaster(privPlugin.p.hartId*intIdPerHart+1))
-      drivers.foreach(node << _)
-    }
-
-    icfs.foreach(_.release())
-
-    val clintPort = clint.createPort(privPlugin.p.hartId)
-    val mti, msi = InterruptNode.slave()
-    mti << clintPort.mti
-    msi << clintPort.msi
-    clint.lock.release()
 
     // Add a plugin to Nax which will handle the negotiation of the tilelink parameters
     l += new Plugin {
@@ -147,9 +126,11 @@ class TilelinkNaxRiscvFiber() extends Area with RiscvHart{
       case p : PrivilegedPlugin => {
         p.io.int.machine.timer := mti.flag
         p.io.int.machine.software := msi.flag
-        p.io.int.machine.external := mei.node.flag
-        if(p.p.withSupervisor) p.io.int.supervisor.external := sei.node.flag
-        if(p.p.withRdTime) p.io.rdtime := clint.thread.core.io.time
+        p.io.int.machine.external := mei.flag
+        if(p.p.withSupervisor) p.io.int.supervisor.external := sei.flag
+        if(p.p.withRdTime) {
+          p.io.rdtime := clint.thread.core.io.time
+        }
       }
       case _ =>
     }

src/main/scala/naxriscv/platform/litex/NaxSoc.scala

@@ -18,7 +18,7 @@ import spinal.lib.bus.tilelink.fabric.Node
 import spinal.lib.cpu.riscv.debug.DebugModuleFiber
 import spinal.lib.misc.plic.TilelinkPlicFiber
 import spinal.lib.misc.{InterruptNode, TilelinkClintFiber}
-import spinal.lib.system.tag.{MappedNode, MemoryConnection, MemoryTransferTag, MemoryTransfers, PMA}
+import spinal.lib.system.tag.{MappedNode, MemoryConnection, MemoryEndpoint, MemoryTransferTag, MemoryTransfers, PMA}
 
 import scala.collection.mutable.ArrayBuffer
 
@@ -47,7 +47,7 @@ class NaxSoc(c : NaxSocConfig) extends Component{
   val system = socResetCtrl.cd on new AreaRoot {
     val mainDataWidth = c.naxPlugins.head.collectFirst { case p: DataCachePlugin => p.memDataWidth }.get
 
-    val naxes = for (p <- naxPlugins) yield new TilelinkNaxRiscvFiber().setPlugins(p)
+    val naxes = for (p <- naxPlugins) yield new TilelinkNaxRiscvFiber(p)
     for (nax <- naxes) {
       nax.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S, b = StreamPipe.HALF, c = StreamPipe.FULL, e = StreamPipe.HALF)
       nax.iBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S)
@@ -113,9 +113,12 @@ class NaxSoc(c : NaxSocConfig) extends Component{
     val toAxi4 = withMem generate new fabric.Axi4Bridge
     if (withMem) {
       toAxi4.up.forceDataWidth(mBusWidth)
+      toAxi4.up << nonCoherent
       toAxi4.down.addTag(PMA.MAIN)
       regions.filter(_.onMemory).foreach(r =>
-        toAxi4.up at r.mapping of nonCoherent
+        toAxi4.down.addTag(new MemoryEndpoint {
+          override def mapping = r.mapping
+        })
       )
     }
 
@@ -158,14 +161,18 @@ class NaxSoc(c : NaxSocConfig) extends Component{
           override def up = toAxiLite4.down
           override def down = self
           override def transformers = Nil
-          override def mapping = region.mapping
+//          override def mapping = region.mapping //TODO
           populate()
         }
+        self.addTag(new MemoryEndpoint {
+          override def mapping = region.mapping
+        })
 
         addTag(new MemoryTransferTag {
           override def get = toAxiLite4.up.m2s.parameters.emits
         })
         if (region.isCachable) addTag(PMA.MAIN)
+        if (region.isExecutable) addTag(PMA.EXECUTABLE)
       }
     }
 
@@ -201,7 +208,7 @@ class NaxSoc(c : NaxSocConfig) extends Component{
       if (withJtagTap) debug.tap.jtag.setName("jtag")
       if (withJtagInstruction) debug.instruction.setName("jtag_instruction")
       if (c.withDebug) {
-        debug.dm.ndmreset.toIo().setName("debug_ndmreset")
+        out(debug.dm.ndmreset).setName("debug_ndmreset")
         debug.cd.reset.setName("debug_reset")
       }
 

src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala

@@ -18,7 +18,7 @@ import spinal.lib.system.tag.PMA
 // SocDemo is a little SoC made only for simulation purposes.
 class SocDemo(cpuCount : Int, withL2 : Boolean = true, asic : Boolean = false, xlen : Int = 32) extends Component {
   // Create a few NaxRiscv cpu
-  val naxes = for(hartId <- 0 until cpuCount) yield new TilelinkNaxRiscvFiber().setCoherentConfig(hartId, asic = asic, xlen = xlen)
+  val naxes = for(hartId <- 0 until cpuCount) yield new TilelinkNaxRiscvFiber(TilelinkNaxRiscvFiber.getCoherentConfig(hartId, asic = asic, xlen = xlen))
 
   // As NaxRiscv may emit memory request to some unmapped memory space, we need to catch those with TransactionFilter
   val memFilter, ioFilter = new fabric.TransferFilter()
@@ -75,11 +75,12 @@ class SocDemo(cpuCount : Int, withL2 : Boolean = true, asic : Boolean = false, x
         )
       )
     )
-    emulated.node << bus
+    emulated.node at(0, 0x1000) of bus
 
     val custom = Fiber build new Area{
       val mei,sei = in Bool()
       naxes.foreach{ hart =>
+        hart.thread.get
         hart.getIntMachineExternal() setWhen mei
         hart.getIntSupervisorExternal() setWhen sei
       }