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@raysalemi
Ray Salemi raysalemi
I am the author of the UVM Primer and the Aerospace & Defense Solutions Manager at Siemens EDA DVT division.

Siemens EDA Boston, MA

@dshekhalev
des00 dshekhalev
@dotcypress
Vitaly Domnikov dotcypress
🇺🇦🇺🇸 OSS/OSH Advocate, console.log Expert.

ДСК

@alexforencich
Alex Forencich alexforencich

UC San Diego La Jolla, CA

@Naixr1m
Naixr1m
RTL Designer. Trying to command pieces of silicon. Range of interest: FPGA, ASIC, CPU, GPU.

Saint-Petersburg

@johan92
Ivan Shevchuk johan92

Saint-Petersburg, Russia

@xupgit
Xilinx University Program xupgit

Xilinx San Jose, CA, USA

@hukenovs
Alexander Kapitanov hukenovs
Data Scientist, ex. FPGA Engineer
@pConst
Konstantin Pavlov pConst
Digital electronics, FPGAs, multi-gigabit interfaces

Saint-Petersburg, Russia

@iDoka
Dmitry Murzinov iDoka
Hardware Imagineer | Digital IC Design Engineer | Automotive Electronics Enthusiast

@dokard @deepware-ai Error: Unable to resolve

@NickolayTernovoy
Nickolay NickolayTernovoy
PhD student at MIET; RTL design engineer; RISC-V, Posit enthusiast; e-mail: nickolay.tern@gmail.com telegram: https://t.me/cpu_design

Semidynamics