D-Class Amplifier

ECEN405 Class-D amplifier group project

Team members:

• Daniel Eisen
• Nickolai Wolfe
• Niels Clayton

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Input Filter Stage

• The input stage will use two active filters, a 10Hz corner frequency high pass filter, and a 200Hz corner frequency low pass filter. This will provide an overall filter passband of 10Hz - 200Hz.

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S-PWM Generation

• It is important to be able to effectively filter out the switching frequency of the sinusoidal pulse width modulated (SPWM) signal output. because of this, we want to ensure that the switching frequency is at least two decades above the maximum output frequency. This will ensure an attenuation of at least 40dB of the switching noise by the output filter.

• Our output frequency range is 10Hz - 200Hz. To achieve the required attenuation of the switching frequency, it will nee to be 20kHz.

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Power Stage

• 2x IR21834PBF drivers
  • V_offset: 600V max
  • I_o+-: 1.4A/1.8A
  • T_on/off: 180ns/220ns
  • MT: 35ns
  • V_cc: 10-20V (single)
  • V_in: Vss+5V
• 4x PHP23NQ11T,127 Fets
  • minimum BV_dss of 45V
  • Actual: 110V
  • Gate Charge Qg: 10nC
  • Rdson: 49m

https://www.infineon.com/dgdl/Infineon-Using_Monolithic_Voltage_Gate_Drivers-AN-v01_00-EN.pdf?fileId=5546d462584d1d4a01585242c11947b1

Output filter

Signal freq max of 200Hz, Switching frequency of ~25kHz Place corner frequency of filter at 2kHz (decade centred) mes

https://datasheets.maximintegrated.com/en/ds/MAX4295.pdf

Figure 4c. Alternate Balanced 2-Pole Filter

Balanced 2-Pole (Figure 4b): A balanced 2-pole filter does not have the common- mode swing problem of the single-ended filter. C = 2 / (√2 ✕ RL ✕ ωo), L = (√2 ✕ RL)/(2 ✕ ωo); choosing fo = 30kHz and RL = 4Ω, C1a = C1b = 2.0μF, L1a = L1b = 15μH. A single capacitor connected across RL, with a value of CL = 1/(√2 ✕ RL ✕ ωo), can be used in place of C1a and C1b. However, the configuration as shown gives an improved rejection to common-mode signal compo- nents of OUT+_ and OUT-_. If the single capacitor scheme is used, additional capacitors (Ca and Cb) can be added from each side of RL, providing a high-fre- quency short to ground (Figure 4c). These capacitors should be approximately 0.2 ✕ CL.