This release increases the number of peripheral routing entries from one to six. The additional peripheral routing entries give SpiNNaker applications more flexibility in the selection of SpiNNaker packet routing keys to send to peripherals.
This version is required on SpiNN-5 boards connected to spif, the SpiNNaker Peripheral Interface. The attached bitfiles are for SpiNN-5 FPGA0, as this is the only one that handles peripheral I/O.
Bitfile spin5_spif_front_1-2-0_220323_id0.bit is intended for use on standalone SpiNN-5 boards. Connect a spif board to the bottom front SATA connector.
Bitfile spin5_spif_back_1-2-0_220323_id0.bit is intended for use on multiboard SpiNNaker systems. Connect a spif board to the middle back SATA connector.
These files can also be used on SpiNN-5 boards not connected to spif, although there is no need to update the FPGA bitfiles on those boards.
The bitfiles were generated using Xilinx ISE version '14.7'.