Merge branch 'main' into asic

# Conflicts:
#	src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala

src/main/scala/naxriscv/execute/BranchPlugin.scala

@@ -128,7 +128,7 @@ class BranchPlugin(val euId : String,
     val branch = new ExecuteArea(branchAt){
       import stage._
 
-      val badEarlyTaken  = if(setup.withBranchContext) BRANCH_EARLY.taken =/= COND              else CombInit(stage(COND))
+      val badEarlyTaken  = if(setup.withBranchContext) BRANCH_EARLY.taken =/= COND else CombInit(stage(COND))
       MISSPREDICTED := badEarlyTaken || COND && BAD_EARLY_TARGET
 
       def target = if(setup.withBranchContext)  stage(PC, "TARGET") else stage(PC, "TRUE")

src/main/scala/naxriscv/platform/NaxriscvProbe.scala

@@ -154,8 +154,10 @@ class NaxriscvProbe(nax : NaxRiscv, hartId : Int){
   def add(tracer : TraceBackend) : this.type = {
     backends += tracer
     tracer.newCpuMemoryView(hartId, lsuPlugin.lqSize+1, lsuPlugin.sqSize) //+1 because AMO
-    tracer.newCpu(hartId, "RV32IMA", "MSU", 32, hartId)
-    tracer.setPc(hartId, 0x80000000)
+    tracer.newCpu(hartId, s"RV${xlen}IMA", "MSU", 32, hartId)
+    var pc = 0x80000000l
+    if(xlen == 32) pc = (pc << 32) >> 32
+    tracer.setPc(hartId, pc)
     this
   }
 

src/main/scala/naxriscv/platform/PeripheralEmulator.scala

@@ -54,7 +54,7 @@ class PeripheralEmulator(bus : tilelink.Bus, mei : Bool, sei : Bool, cd : ClockD
         a.address.toInt match {
           case IO_FAULT_ADDRESS => {
             d.denied = true
-            Random.nextBytes(d.data)
+            simRandom.nextBytes(d.data)
           }
           case GETC => {
             if(System.in.available() != 0) {

src/main/scala/naxriscv/platform/TilelinkNaxRiscvFiber.scala

@@ -52,15 +52,16 @@ class TilelinkNaxRiscvFiber() extends Area with RiscvHart{
     this.clint load clint
   }
 
-  def setCoherentConfig(hartId : Int, asic : Boolean = false) : this.type = {
+  def setCoherentConfig(hartId : Int, asic : Boolean = false, xlen : Int = 32) : this.type = {
     plugins load Config.plugins(
       withCoherency = true,
       withRdTime = false,
       aluCount = 2,
       decodeCount = 2,
       ioRange = a => a(31 downto 28) === 0x1,
       hartId = hartId,
-      asic = asic
+      asic = asic,
+      xlen = xlen
     )
     this
   }

src/main/scala/naxriscv/platform/litex/NaxSoc.scala

@@ -104,6 +104,7 @@ class NaxSoc(c : NaxSocConfig) extends Component{
       cache.parameter.cacheBytes = l2Bytes
       cache.up << memFilter.down
       cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL, d = StreamPipe.FULL)
+      cache.down.setDownConnection(d = StreamPipe.S2M)
       cache.down.forceDataWidth(mainDataWidth)
       nonCoherent = cache.down
     }

src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala

@@ -1,5 +1,6 @@
 package naxriscv.platform.tilelinkdemo
 
+import naxriscv.lsu.DataCachePlugin
 import naxriscv.platform.{RvlsBackend, TilelinkNaxRiscvFiber}
 import riscv.model.Model
 import spinal.core._
@@ -15,9 +16,9 @@ import spinal.lib.misc.plic.TilelinkPlicFiber
 import spinal.lib.system.tag.PMA
 
 // SocDemo is a little SoC made only for simulation purposes.
-class SocDemo(cpuCount : Int, withL2 : Boolean = true, asic : Boolean = false) extends Component {
+class SocDemo(cpuCount : Int, withL2 : Boolean = true, asic : Boolean = false, xlen : Int = 32) extends Component {
   // Create a few NaxRiscv cpu
-  val naxes = for(hartId <- 0 until cpuCount) yield new TilelinkNaxRiscvFiber().setCoherentConfig(hartId, asic = asic)
+  val naxes = for(hartId <- 0 until cpuCount) yield new TilelinkNaxRiscvFiber().setCoherentConfig(hartId, asic = asic, xlen = xlen)
 
   // As NaxRiscv may emit memory request to some unmapped memory space, we need to catch those with TransactionFilter
   val memFilter, ioFilter = new fabric.TransferFilter()

src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala

@@ -57,11 +57,13 @@ object SocSim extends App {
   var asic = false
   var iverilog = false
   var naxCount = 1
+  var xlen = 32
   val bins = ArrayBuffer[(Long, String)]()
   val elfs = ArrayBuffer[String]()
 
   assert(new scopt.OptionParser[Unit]("NaxRiscv") {
     help("help").text("prints this usage text")
+    opt[Int]("xlen") action { (v, c) => xlen = v }
     opt[Unit]("dual-sim") action { (v, c) => dualSim = true }
     opt[Unit]("trace") action { (v, c) => traceIt = true }
     opt[Unit]("no-rvls") action { (v, c) => withRvls = false }
@@ -88,7 +90,7 @@ object SocSim extends App {
 //  sc.addSimulatorFlag("--prof-exec")
 
   // Tweek the toplevel a bit
-  class SocDemoSim(cpuCount : Int) extends SocDemo(cpuCount, withL2 = withL2, asic = asic){
+  class SocDemoSim(cpuCount : Int) extends SocDemo(cpuCount, withL2 = withL2, asic = asic, xlen = xlen){
     setDefinitionName("SocDemo")
     // You can for instance override cache parameters of the CPU caches like that :
     naxes.flatMap(_.plugins).foreach{
@@ -165,7 +167,7 @@ object SocSim extends App {
     }
 
     // Collect traces from the CPUs behaviour
-    val naxes = withRvls generate dut.naxes.map(nax => new NaxriscvTilelinkProbe(nax, nax.getHartId()))
+    val naxes = (!iverilog) generate dut.naxes.map(nax => new NaxriscvTilelinkProbe(nax, nax.getHartId()))
     if(withRvls) naxes.foreach(_.add(rvls))
 
     // Things to enable when we want to collect traces
@@ -176,12 +178,12 @@ object SocSim extends App {
       val tracerFile = new FileBackend(new File(new File(compiled.compiledPath, currentTestName), "tracer.log"))
       tracerFile.spinalSimFlusher(10 * 10000)
       tracerFile.spinalSimTime(10000)
-//      naxes.foreach { hart =>
-//        hart.add(tracerFile)
-//        val r = hart.backends.reverse
-//        hart.backends.clear()
-//        hart.backends ++= r
-//      }
+      if(naxes != null) naxes.foreach { hart =>
+        hart.add(tracerFile)
+        val r = hart.backends.reverse
+        hart.backends.clear()
+        hart.backends ++= r
+      }
     }
 
     // Load the binaries
@@ -192,27 +194,30 @@ object SocSim extends App {
 
     // load elfs
     for (file <- elfs) {
-      val elf = new Elf(new File(file))
-      elf.load(ma.mem, -0xffffffff80000000l)
+      val elf = new Elf(new File(file), xlen)
+      elf.load(ma.mem, 0x80000000l)
       if(withRvls) rvls.loadElf(0, elf.f)
 
       if(elf.getELFSymbol("pass") != null && elf.getELFSymbol("fail") != null) {
         val passSymbol = elf.getSymbolAddress("pass")
         val failSymbol = elf.getSymbolAddress("fail")
-//        naxes.foreach { nax =>
-//          nax.commitsCallbacks += { (hartId, pc) =>
-//            if (pc == passSymbol) delayed(1) {
-//              dut.naxes.flatMap(_.plugins).foreach {
-//                case p: FetchCachePlugin => println("i$ refill = " + p.logic.refill.pushCounter.toLong)
-//                case p: DataCachePlugin => println("d$ refill = " + p.logic.cache.refill.pushCounter.toLong)
-//                case _ =>
-//              }
-//
-//              simSuccess()
-//            }
-//            if (pc == failSymbol) delayed(1)(simFailure("Software reach the fail symbole :("))
-//          }
-//        }
+        if(naxes != null) naxes.foreach { nax =>
+          nax.commitsCallbacks += { (hartId, pc) =>
+            if (pc == passSymbol) delayed(1) {
+              dut.naxes.foreach { nax =>
+                println(s"Hart $hartId")
+                nax.plugins.foreach {
+                  case p: FetchCachePlugin => println("- i$ refill = " + p.logic.refill.pushCounter.toLong)
+                  case p: DataCachePlugin => println("- d$ refill = " + p.logic.cache.refill.pushCounter.toLong)
+                  case _ =>
+                }
+              }
+
+              simSuccess()
+            }
+            if (pc == failSymbol) delayed(1)(simFailure("Software reach the fail symbole :("))
+          }
+        }
       }
     }
 

src/main/scala/spinal/lib/misc/Elf.scala

@@ -6,7 +6,7 @@ import spinal.lib.sim.SparseMemory
 import java.io.File
 import java.nio.file.Files
 
-class Elf(val f : File){
+class Elf(val f : File, addressWidth : Int){
   val fBytes = Files.readAllBytes(f.toPath)
   val elf = ElfFile.from(fBytes)
 
@@ -35,7 +35,7 @@ class Elf(val f : File){
     foreachSection{section =>
       if((section.header.sh_flags & ElfSectionHeader.FLAG_ALLOC) != 0){
         val data = getData(section)
-        val memoryAddress = section.header.sh_addr + offset
+        val memoryAddress = (section.header.sh_addr - offset) & ((BigInt(1) << addressWidth)-1).toLong
         mem.write(memoryAddress, data)
       }
     }
@@ -85,7 +85,7 @@ class Elf(val f : File){
 
 object ElfTest extends App{
   import net.fornwall.jelf._
-  val elf = new Elf(new File("ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf"))
+  val elf = new Elf(new File("ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf"), 32)
 
   elf.foreachSection{section =>
     println(f"${section.header.getName} ${section.header.sh_type} ${section.header.sh_flags}")

src/test/cpp/naxriscv/README.md

@@ -8,7 +8,6 @@ SPDX-License-Identifier: CC0-1.0
 
 ```shell
 # Get the repo
-git clone https://github.com/SpinalHDL/SpinalHDL.git --recursive
 git clone https://github.com/SpinalHDL/NaxRiscv.git --recursive
 cd NaxRiscv
 export NAXRISCV=${PWD}

src/test/scala/naxriscv/Rvls.scala

@@ -0,0 +1,10 @@
+package naxriscv
+
+object Rvls extends App{
+  import rvls.jni.Frontend
+
+  val handle = Frontend.newDisassemble(32)
+  println(Frontend.disassemble(handle, 0x03410793))
+  println(Frontend.disassemble(handle, 0x13))
+  Frontend.deleteDisassemble(handle)
+}