improve NaxSoc timings

SpinalHDL · Nov 14, 2023 · ec3ee4d · ec3ee4d
1 parent d07064a
commit ec3ee4d
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/src/main/scala/naxriscv/platform/litex/NaxSoc.scala b/src/main/scala/naxriscv/platform/litex/NaxSoc.scala
@@ -104,6 +104,7 @@ class NaxSoc(c : NaxSocConfig) extends Component{
       cache.parameter.cacheBytes = l2Bytes
       cache.up << memFilter.down
       cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL, d = StreamPipe.FULL)
+      cache.down.setDownConnection(d = StreamPipe.S2M)
       cache.down.forceDataWidth(mainDataWidth)
       nonCoherent = cache.down
     }