Sync asic stuff with the doc

SpinalHDL · Jan 16, 2024 · f630e63 · f630e63
1 parent 9fb1618
commit f630e63
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Showing 2 changed files with 29 additions and 15 deletions.
diff --git a/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala b/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala
@@ -46,20 +46,28 @@ object NaxAsicGen extends App{
       //      withCoherency = true,
       ioRange = a => a(31 downto 28) === 0x1// || !a(12)//(a(5, 6 bits) ^ a(12, 6 bits)) === 51
     )
+
     l.foreach{
       case p : EmbeddedJtagPlugin => p.debugCd.load(ClockDomain.current.copy(reset = Bool().setName("debug_reset")))
-
-      case p: FetchCachePlugin => p.wayCount = 2; p.cacheSize = 4096; p.memDataWidth = 64
-      case p: DataCachePlugin => p.wayCount = 2; p.cacheSize = 4096; p.memDataWidth = 64
-      case p: BtbPlugin => p.entries = 64
-      case p: GSharePlugin => p.memBytes = 512
-
-//      case p: FetchCachePlugin => p.wayCount = 1; p.cacheSize = 256; p.memDataWidth = 64
-//      case p: DataCachePlugin => p.wayCount = 1; p.cacheSize = 256; p.memDataWidth = 64
-//      case p: BtbPlugin => p.entries = 8
-//      case p: GSharePlugin => p.memBytes = 32
       case _ =>
     }
+
+    target match {
+      case "asic" => l.foreach {
+        case p: FetchCachePlugin => p.wayCount = 1; p.cacheSize = 256; p.memDataWidth = 64
+        case p: DataCachePlugin => p.wayCount = 1; p.cacheSize = 256; p.memDataWidth = 64
+        case p: BtbPlugin => p.entries = 8
+        case p: GSharePlugin => p.memBytes = 32
+        case _ =>
+      }
+      case "sky130" => l.foreach {
+        case p: FetchCachePlugin => p.wayCount = 2; p.cacheSize = 4096; p.memDataWidth = 64
+        case p: DataCachePlugin => p.wayCount = 2; p.cacheSize = 4096; p.memDataWidth = 64
+        case p: BtbPlugin => p.entries = 64
+        case p: GSharePlugin => p.memBytes = 512
+        case _ =>
+      }
+    }
     l
   }
 

diff --git a/src/main/scala/naxriscv/platform/asic/Sky130.scala b/src/main/scala/naxriscv/platform/asic/Sky130.scala
@@ -1,6 +1,7 @@
 
 package naxriscv.platform.asic
 import naxriscv.compatibility.MultiPortWritesSymplifier
+import org.apache.commons.io.FileUtils
 import spinal.core._
 import spinal.core.internals.{MemTopology, PhaseContext, PhaseMemBlackBoxingWithPolicy, PhaseNetlist}
 import spinal.lib._
@@ -85,9 +86,14 @@ class OpenRamPhase extends PhaseNetlist {
 
     val macros = ArrayBuffer[String]()
     println("Generate openram macros")
+
+
     for(c <- configs_1r1w){
       macros += c.name
-      val bf = new BufferedWriter(new FileWriter(new File(c.name + ".py")))
+      val dir = new File(s"sram")
+      FileUtils.forceMkdir(dir)
+
+      val bf = new BufferedWriter(new FileWriter(new File(dir, c.name + ".py")))
       val mask = c.bitPerMask match {
         case Some(x) => s"write_size = $x"
         case None => ""
@@ -123,7 +129,7 @@ class OpenRamPhase extends PhaseNetlist {
 
       bf.close()
 
-      val sbf = new BufferedWriter(new FileWriter(new File(c.name + "_sc.py")))
+      val sbf = new BufferedWriter(new FileWriter(new File(dir, c.name + "_sc.py")))
       sbf.write(
         s"""import siliconcompiler
            |
@@ -146,7 +152,7 @@ class OpenRamPhase extends PhaseNetlist {
       )
       sbf.close()
 
-      val bbf = new BufferedWriter(new FileWriter(new File(c.name + ".bb.v")))
+      val bbf = new BufferedWriter(new FileWriter(new File(dir, c.name + ".bb.v")))
 
       bbf.write(
         s"""// OpenRAM SRAM model
@@ -196,9 +202,9 @@ class OpenRamPhase extends PhaseNetlist {
     println(macros.mkString(" \\\n"))
 
     {
-      val f = new File("openram.sh")
+      val f = new File("sram/openram.sh")
       val bf = new BufferedWriter(new FileWriter(f))
-      bf.write(s"make -j$$(nproc) ${macros.mkString(" ")}")
+      bf.write(s"make ${macros.mkString(" ")}") // -j$$(nproc)
       bf.close()
     }