L2 cache refill

[SoCScholar]

Dear Charles,

How do I add an L2 Data cache refill counter within withL2 block ?

    val scope = new ScopeFiber()
    scope.up at 0x04000000 of peripheral.bus
    if(withL2) {
      scope.add(l2.cache.logic.cache.events.acquire.hit, 0xF00)  //acquire is used by data cache
      scope.add(l2.cache.logic.cache.events.acquire.miss, 0xF04)
      scope.add(l2.cache.logic.cache.events.getPut.hit, 0xF20)   //getPut is used by instruction cache refill and DMA
      scope.add(l2.cache.logic.cache.events.getPut.miss, 0xF24)
    }

I guess this is for L1 cache

   for((nax, i) <- naxes.zipWithIndex) nax.plugins.foreach {
     case p: FetchCachePlugin => scope.add(p.logic.refill.fire, i*0x80 + 0x000)
     case p: DataCachePlugin => {
       scope.add(p.logic.cache.refill.push.fire, i * 0x80 + 0x010)
       scope.add(p.logic.cache.writeback.push.fire, i * 0x80 + 0x014)
     }
     case _ =>
   }
 }
 

In addition to the L2 cache miss counter, is SCOPE_HART_DCACHE_REFILL for L1 Dcache inside ext/NaxSoftware/baremetal/socdemo ?

#define SCOPE_HART_DCACHE_REFILL 0x10

    //read SCOPE_HART0_DCACHE_REFILL
    la x1, SCOPE_HART0 + SCOPE_HART_DCACHE_REFILL
    lw x10, 0(x1)

Thank you so much :)

[Dolu1990]

Hi,

scope.add(l2.cache.logic.cache.events.acquire.miss, 0xF04) will add a counter which will count cache refills triggered by d$
scope.add(l2.cache.logic.cache.events.getPut.miss, 0xF24) will add a counter which will count cache refills triggeres by i$ and dma accesses

You want to combine the two ?

I guess this is for L1 cache

yes

SCOPE_HART_DCACHE_REFILL for L1 Dcache inside

Yes

[SoCScholar]

Is it possible add an L2 Data cache refill counter within withL2 block ?

[Dolu1990]

Is it possible add an L2 Data cache refill counter within withL2 block ?

I don't understand

    if(withL2) {
      scope.add(l2.cache.logic.cache.events.acquire.miss, 0xF04)
      scope.add(l2.cache.logic.cache.events.getPut.miss, 0xF24)  //they are already there
    }

You can create a unified counter by doing :

      scope.add(l2.cache.logic.cache.events.acquire.miss.pull() || l2.cache.logic.cache.events.getPut.miss.pull(), 0xF30)

[SoCScholar]

thank you so much :)

i was wondering about L2 cache refill counter

below seems like miss counter only

    if(withL2) {
      scope.add(l2.cache.logic.cache.events.acquire.miss, 0xF04)
      scope.add(l2.cache.logic.cache.events.getPut.miss, 0xF24)  //they are already there
    }
    
    ```

[Dolu1990]

1 miss => 1 refill (for the current config), so they are the same

[SoCScholar]

Will it be possible to measure L2 miss counter of specific core from L2 cache ?

[Dolu1990]

Will it be possible to measure L2 miss counter of specific core from L2 cache ?

Ahhh yes it is. i reworked the Scope stuff a bit, here it is :
504641d#diff-f63c34d68d437c149a52f157ab95a68cf793ce488f6ef56a58c7a3ab8018e04aR114

[SoCScholar]

Thank you so much :)

May be it will nice to update the picture in L2 cache in documentation so it will be easy to understand any user How does L2 cache is working.

like we now have like MSHR (miss status holding register ) from each core in L2 cache.

https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/memory/index.html

[Dolu1990]

like we now have like MSHR (miss status holding register ) from each core in L2 cache.

Those are very very experimental things, just for the SoC simulation, it may change soon, not sure it is good to document them, until there is a good final version.