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Issues: SpinalHDL/NaxRiscv
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[BUG] A trap is triggered when the pmpcfg register is read by csrr
#110
opened Jun 28, 2024 by
Bill94l
updated Jun 28, 2024
Does NaxRiscv update mtval after trap illegal_inst?
#107
opened May 31, 2024 by
zhangkanqi
updated May 31, 2024
how to run a nax_core with a AXI4 interface
#81
opened Feb 23, 2024 by
duanjiulon
updated Apr 25, 2024
Request for Guidance: Starting with a Minimal Framework
#71
opened Dec 27, 2023 by
skylayer
updated Apr 19, 2024
Error in implementation of SRAW and SRAIW instructions
#95
opened Apr 12, 2024 by
Nanotrust
updated Apr 12, 2024
L1/L2 cache and integration with CPU pipeline
#91
opened Apr 8, 2024 by
SoCSavant
updated Apr 11, 2024
Read a sram that is changed by other host
#90
opened Apr 8, 2024 by
zyn810039594
updated Apr 9, 2024
cache_throttling && dirty evicts counting.
#87
opened Mar 11, 2024 by
SoCSavant
updated Mar 26, 2024
[BUG] CSR write verification error in the Verilator wrapper
#78
opened Jan 26, 2024 by
Bill94l
updated Feb 26, 2024
Default branch direction prediction should be TAKEN (currently NOT TAKEN)
#79
opened Jan 30, 2024 by
ronan-lashermes
updated Jan 30, 2024
NaxRiscv running custom test cases prompts FAILURE ???
#72
opened Jan 3, 2024 by
LMiaoH
updated Jan 17, 2024
Failing to reproduce the NaxRiscv/Debian setup
#69
opened Nov 15, 2023 by
newinnovations
updated Dec 15, 2023
L2 cache writeback Counter of specific core
#61
opened Nov 4, 2023 by
SoCSavant
updated Nov 14, 2023
threshold of maxiumum count of Naxcore that can be possible to simulate ?
#62
opened Nov 6, 2023 by
SoCSavant
updated Nov 10, 2023
integrating both L2 cache miss counter and throttle
#58
opened Oct 29, 2023 by
SoCSavant
updated Nov 6, 2023
Performance counters and custom opensbi
#40
opened Jul 25, 2023 by
denishoornaert
updated Aug 9, 2023
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