Update riscv-arch-test

riscv-arch-test/README.md

@@ -1,23 +1,34 @@
+# RISCV-ARCH-TEST
 
-```shell
-git clone https://github.com/SpinalHDL/riscv-compliance.git --branch naxriscv riscv-arch-test 
-cd riscv-arch-test
+This directory contains built riscv-arch-tests and scripts to update the binaries.
 
-export RISCV_TARGET=naxriscv
-export XLEN=32
 
-make RISCV_DEVICE=I compile
-make RISCV_DEVICE=M compile
-make RISCV_DEVICE=C compile
-make RISCV_DEVICE=Zifencei compile
-make RISCV_DEVICE=privilege compile
+A recent riscv compiler is needed (packages for Ubuntu, for other systems refer to riscv-gnu-toolchain docs).
+```shell
+sudo apt-get install \
+  autoconf automake autotools-dev curl \
+  python3 python3-pip python-is-python3 \
+  libmpc-dev libmpfr-dev libgmp-dev gawk build-essential \
+  bison flex texinfo gperf libtool patchutils bc zlib1g-dev \
+  libexpat-dev ninja-build git cmake libglib2.0-dev
+git clone --recursive https://github.com/riscv-collab/riscv-gnu-toolchain.git
+cd riscv-gnu-toolchain
+git checkout 2023.12.20
+./configure --prefix=/opt/riscv64-unknown-elf-gcc-2023.12.20
+sudo make -j16 all
+```
 
-export RISCV_TARGET=naxriscv
-export XLEN=64
+With the compiler available we can update the test binaries:
+```shell
+export PATH=/opt/riscv64-unknown-elf-gcc-2023.12.20/bin:$PATH
+# can be checked out somewhere else
+git clone https://github.com/riscv-non-isa/riscv-arch-test.git
+cd riscv-arch-test
+git checkout 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
+cd ..
+# pass path to suite folder
+./build.py riscv-arch-test/riscv-test-suite
+```
 
-make RISCV_DEVICE=I compile
-make RISCV_DEVICE=M compile
-make RISCV_DEVICE=C compile
-make RISCV_DEVICE=Zifencei compile
-make RISCV_DEVICE=privilege compile
-```
+The tests built depend on the settings in `build.py`, currently the script needs
+to be adapted for changes.

riscv-arch-test/build.py

@@ -0,0 +1,157 @@
+#!/usr/bin/env python3
+import re
+import subprocess
+import os
+import pathlib
+import sys
+
+PREFIX = 'riscv64-unknown-elf-'
+GCC = PREFIX + 'gcc'
+OBJDUMP = PREFIX + 'objdump'
+
+BASE_GCC_OPTS = [
+    '-static',
+    '-mcmodel=medany',
+    '-g',
+    '-fvisibility=hidden',
+    '-nostdlib',
+    '-nostartfiles',
+    '-Wl,--no-warn-rwx-segments',
+    '-I.'
+]
+
+RED = '\x1b[1;31m'
+GREEN = '\x1b[1;32m'
+CLEAR = '\x1b[0m'
+
+
+def make_march(isa:str) -> str:
+    xlen = isa[2:4]
+    march = 'rv' + xlen
+    if "I" in isa:
+        march += 'i'
+    if "M" in isa:
+        march += 'm'
+    if "A" in isa:
+        march += 'a'
+    if "F" in isa:
+        march += 'f'
+    if "D" in isa:
+        march += 'd'
+    if "C" in isa:
+        march += 'c'
+    if "Zicsr" in isa:
+        march += '_zicsr'
+    if "Zifencei" in isa:
+        march += '_zifencei'
+    if "Zca" in isa:
+        march += '_zca' 
+    if "Zcb" in isa:
+        march += '_zcb'  
+    if "Zba" in isa:
+        march += '_zba'
+    if "Zbb" in isa:
+        march += '_zbb'
+    if "Zbc" in isa:
+        march += '_zbc'    
+    if "Zbs" in isa:
+        march += '_zbs'
+    return march, xlen
+
+
+def build_info(file, arch, hw_misaligned):
+    build_isa = None
+    defs = []
+    with open(file, 'r') as f:
+        for line in f:
+            if 'RVTEST_ISA' in line:
+                build_isa = line.split('"')[1]
+
+            if 'RVTEST_CASE' in line:
+                # parsing e.g. RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
+                _, things, _ = line.split(',')
+
+                things = things[len('"//'):-1] # remove "// and trailing
+                for c in things.split(';'):
+                    c = c.strip()
+                    if c.startswith('check ISA:=regex('):                 
+                        regex = c[len('check ISA:=regex('):-1]
+                        if re.match(regex, arch) is None:
+                            print(f'{RED}SKIP{CLEAR}  {file} :: {c}')
+                            return False, None, None
+
+                    elif c.startswith('def '):
+                        defs.append(c[len('def '):])
+
+                    elif c == 'check hw_data_misaligned_support:=True':
+                        if not hw_misaligned:
+                            print(f'{RED}SKIP{CLEAR}  {file} :: {c}')
+                            return False, None, None
+
+                    elif c == '':
+                        pass
+
+                    else:
+                        raise Exception(f"don't understand string: {c} in {file}")
+
+                print(f'{GREEN}BUILD{CLEAR} {file}')
+                return True, build_isa, defs
+
+
+def build(inp, outp, suite, isa, defs):
+    march, xlen = make_march(isa)
+    mabi = 'ilp32' if xlen == '32' else 'lp64'
+    if 'D' in isa:
+        mabi += 'd'
+    elif 'F' in isa:
+        mabi += 'f'
+    flen = '64' if 'D' in isa else '32'
+
+    subprocess.run([
+            GCC,
+            *BASE_GCC_OPTS,
+            f'-I{suite}/env',
+            f'-march={march}',
+            f'-mabi={mabi}',
+            f'-DXLEN={xlen}',
+            f'-DFLEN={flen}',
+            *['-D' + s for s in defs],
+            '-Tlinkmono.ld',
+            inp, 
+            '-o',
+            outp
+        ], check=True)
+    with open(f'{outp}.dis.S', 'w') as f:
+        subprocess.run([OBJDUMP, '--source', outp], stdout=f, check=True)
+
+
+def build_folder(suite, folder, out, isa, hw_misaligned):
+    isa = isa.replace('G', 'IMAFDZicsrZifencei')
+    for file in os.listdir(os.path.join(suite, folder, 'src')):
+        do, build_isa, defs = build_info(os.path.join(suite, folder, 'src', file), isa, hw_misaligned)
+        if do:
+            pathlib.Path(os.path.join(out, folder)).mkdir(parents=True, exist_ok=True)
+            build(
+                os.path.join(suite, folder, 'src', file),
+                os.path.join(out, folder, file[:-2] + '.elf'),
+                suite,
+                build_isa,
+                defs
+            )
+
+
+def main():
+    suite = sys.argv[1]
+
+    for xlen in ['32', '64']:
+        group, isa = f'rv{xlen}i_m', f'RV{xlen}IMCZicsrZifenceiZbaZbbZbcZbs'
+        for ext in os.listdir(os.path.join(suite, group)):
+            if ext.startswith('.'):
+                continue
+
+            print(f'>>> {group} - {ext} - {isa}')
+            build_folder(suite, os.path.join(group, ext), '.', isa, hw_misaligned=True)
+
+
+if __name__ == '__main__':
+    main()

riscv-arch-test/linkmono.ld

@@ -0,0 +1,17 @@
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text.init : { *(.text.init) }
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .data.string : { *(.data.string) }
+  .bss : { *(.bss) }
+  _end = .;
+}

riscv-arch-test/model_test.h

@@ -0,0 +1,160 @@
+#ifndef _COMPLIANCE_MODEL_H
+#define _COMPLIANCE_MODEL_H
+
+#define RVMODEL_DATA_SECTION \
+        .pushsection .tohost,"aw",@progbits;                            \
+        .align 8; .global tohost; tohost: .dword 0;                     \
+        .align 8; .global fromhost; fromhost: .dword 0;                 \
+        .popsection;                                                    \
+        .align 8; .global begin_regstate; begin_regstate:               \
+        .word 128;                                                      \
+        .align 8; .global end_regstate; end_regstate:                   \
+        .word 4;
+
+
+//TODO: Add code here to run after all tests have been run
+// The .align 4 ensures that the signature begins at a 16-byte boundary
+#define RVMODEL_HALT                                              \
+  la x1, begin_signature;       \
+  la x2, end_signature;          \
+check_loop:  ;                   \
+  lw x3, 0(x1);                  \
+  addi x1, x1, 4;                \
+  bne x1, x2, check_loop;      \
+pass: ;                           \
+  nop;                           \
+  self_loop:  j self_loop;
+
+//TODO: declare the start of your signature region here. Nothing else to be used here.
+// The .align 4 ensures that the signature ends at a 16-byte boundary
+#define RVMODEL_DATA_BEGIN                                              \
+  .align 4; .global begin_signature; begin_signature:
+
+//TODO: declare the end of the signature region here. Add other target specific contents here.
+#define RVMODEL_DATA_END                                                      \
+  .align 4; .global end_signature; end_signature:                             \
+  RVMODEL_DATA_SECTION                                                        
+
+
+
+//RVMODEL_BOOT
+//TODO:Any specific target init code should be put here or the macro can be left empty
+
+// For code that has a split rom/ram area
+// Code below will copy from the rom area to ram the 
+// data.strings and .data sections to ram.
+// Use linksplit.ld 
+#define RVMODEL_BOOT \
+.section .text.init; \
+.globl _start;      \
+_start:                \
+
+
+// _SP = (volatile register)
+//TODO: Macro to output a string to IO
+#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
+#define RVMODEL_IO_WRITE_STR(_SP, _STR)                                 \
+    .section .data.string;                                              \
+20001:                                                                  \
+    .string _STR;                                                       \
+    .section .text.init;                                                \
+    la a0, 20001b;                                                      \
+    jal FN_WriteStr;
+
+#define RSIZE 4
+// _SP = (volatile register)
+#define LOCAL_IO_PUSH(_SP)                                              \
+    la      _SP,  begin_regstate;                                       \
+    sw      ra,   (1*RSIZE)(_SP);                                       \
+    sw      t0,   (2*RSIZE)(_SP);                                       \
+    sw      t1,   (3*RSIZE)(_SP);                                       \
+    sw      t2,   (4*RSIZE)(_SP);                                       \
+    sw      t3,   (5*RSIZE)(_SP);                                       \
+    sw      t4,   (6*RSIZE)(_SP);                                      \
+    sw      s0,   (7*RSIZE)(_SP);                                      \
+    sw      a0,   (8*RSIZE)(_SP);
+
+// _SP = (volatile register)
+#define LOCAL_IO_POP(_SP)                                               \
+    la      _SP,   begin_regstate;                                      \
+    lw      ra,   (1*RSIZE)(_SP);                                       \
+    lw      t0,   (2*RSIZE)(_SP);                                       \
+    lw      t1,   (3*RSIZE)(_SP);                                       \
+    lw      t2,   (4*RSIZE)(_SP);                                       \
+    lw      t3,   (5*RSIZE)(_SP);                                       \
+    lw      t4,   (6*RSIZE)(_SP);                                       \
+    lw      s0,   (7*RSIZE)(_SP);                                       \
+    lw      a0,   (8*RSIZE)(_SP);
+
+//RVMODEL_IO_ASSERT_GPR_EQ
+// _SP = (volatile register)
+// _R = GPR
+// _I = Immediate
+// This code will check a test to see if the results 
+// match the expected value.
+// It can also be used to tell if a set of tests is still running or has crashed
+#if 1
+#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+
+#elif 0
+// Spinning | =  "I am alive" 
+#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)                                 \
+    LOCAL_IO_PUSH(_SP)                                                  \
+    RVMODEL_IO_WRITE_STR2("|");                                       \
+    RVMODEL_IO_WRITE_STR2("\b=\b");                                       \
+    LOCAL_IO_POP(_SP)
+
+#else
+
+// Test to see if a specific test has passed or not.  Can assert or not.
+#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)                                 \
+    LOCAL_IO_PUSH(_SP)                                                  \
+    mv          s0, _R;                                                 \
+    li          t5, _I;                                                 \
+    beq         s0, t5, 20002f;                                         \
+    LOCAL_IO_WRITE_STR("Test Failed ");                              \
+    LOCAL_IO_WRITE_STR(": ");                                        \
+    LOCAL_IO_WRITE_STR(# _R);                                        \
+    LOCAL_IO_WRITE_STR("( ");                                        \
+    mv      a0, s0;                                                     \
+    jal FN_WriteNmbr;                                                   \
+    LOCAL_IO_WRITE_STR(" ) != ");                                    \
+    mv      a0, t5;                                                     \
+    jal FN_WriteNmbr;                                                   \
+    j 20003f;                                                           \
+20002:                                                                  \
+    LOCAL_IO_WRITE_STR("Test Passed ");                              \
+20003:                                                                  \
+    LOCAL_IO_WRITE_STR("\n");                                        \
+    LOCAL_IO_POP(_SP)
+
+#endif
+
+.section .text
+// FN_WriteStr: Add code here to write a string to IO
+// FN_WriteNmbr: Add code here to write a number (32/64bits) to IO
+FN_WriteStr: \
+    ret; \
+FN_WriteNmbr: \
+    ret;
+
+//RVTEST_IO_ASSERT_SFPR_EQ
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+//RVTEST_IO_ASSERT_DFPR_EQ
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+// TODO: specify the routine for setting machine software interrupt
+#define RVMODEL_SET_MSW_INT
+
+// TODO: specify the routine for clearing machine software interrupt
+#define RVMODEL_CLEAR_MSW_INT
+
+// TODO: specify the routine for clearing machine timer interrupt
+#define RVMODEL_CLEAR_MTIMER_INT
+
+// TODO: specify the routine for clearing machine external interrupt
+#define RVMODEL_CLEAR_MEXT_INT
+
+#endif // _COMPLIANCE_MODEL_H
+
+