v1.10.2

What's Changed

• Fix RegIf SpinalEnum by @yportne13 in #1300
• regif intr-Factory add MASK split SET/CLR feature by @jijingg in #1329
• Compile tester with compiler plugin in Mill by @KireinaHoro in #1325
• StreamMux with stream select use join by @g0t00 in #1308
• Handle Quotes in Attribute values by @g0t00 in #1333
• Some little change on inout signal by @yportne13 in #1319
• Add exit() to StateMachine class by @AtaraxiaZ in #1332
• make cutLongExpressions optional by @yportne13 in #1338
• RegIf: Fix invalid HTML in DocTemplate by @Tectu in #1348
• Axi4Master fixes by @KireinaHoro in #1345
• UnionElement simGet by @KireinaHoro in #1344
• BlackBox Generic update by @jijingg in #1356
• update links for chinese documentation. by @Readon in #1357
• Resize StateDelay cycleCount, fixing width mismatch by @andreasWallner in #1362
• Add messages to asserts in Utils by @andreasWallner in #1361
• Report when a timeout has happened for BusSlaveFactory.readStreamBlockCycles by @KireinaHoro in #1351
• If the output is not connected, set it to be an empty pair of parentheses by @yportne13 in #1339
• Proof of concept for isunknown usage by @jdavidberger in #1352
• Tilelink mapping rework by @Dolu1990 in #1305
• AXI lite simulation master by @KireinaHoro in #1370
• Add CountLeadingZeroes utility function by @fayalalebrun in #1359
• Allow bus slave factory to read mem with an offset by @KireinaHoro in #1371
• Fix corner case of readStreamBlockCycles by @KireinaHoro in #1367
• Wishbone bus bugfixes by @jdavidberger in #1312
• Inline output signal by @yportne13 in #1374
• Rename FlowByCCToggle, deprecating the old name by @andreasWallner in #1360
• Add tag to keep I/O unchanged in InOutWrapper by @andreasWallner in #1373
• Fix simulator flags not passed to elaboration for GHDL by @fayalalebrun in #1363
• Fix typos in Phase.scala by @IanBoyanZhang in #1385
• Fix bin files passed to .sby read statement by @fayalalebrun in #1389
• inline more output signal, such as .xxx(xxx[0]) by @yportne13 in #1383
• add an option to remove timescale by @yportne13 in #1388
• Add test for formal with RAM initial contents by @fayalalebrun in #1390
• add system verilog interface support by @yportne13 in #1364
• couple of minor optimize for verilog code format by @jijingg in #1393
• Update SdramCtrl.scala by @march1993 in #1395
• Priority mux by @Readon in #1377
• Moving simulation temporary builds to Workspace Path by @mrberman87 in #1394
• avoid to use unnamed workspace name while do formal verification. by @Readon in #1397
• Add offset field to generated regif json by @fayalalebrun in #1400
• Add wave prefix for verilator & VCS by @andreasWallner in #1402
• fix sv Interface filelist error by @yportne13 in #1403
• AFix: Adding a few QFormat helpers by @mrberman87 in #1399
• Fix verilator version parsing by @fayalalebrun in #1401
• Add BRAM RegIf support; Add BRAMDriver by @fayalalebrun in #1386
• Fix spaces in file paths for sby generation by @fayalalebrun in #1412
• use a simplified and unified method to get class name. by @Readon in #1413
• jtagvpi: Don't use blocking IO, to avoid blocking the simulation by @rpls in #1350
• Streamhistory by @Readon in #1414
• Correct frequency calculation in newSlowedClockDomain by @louiecaulfield in #1423
• Change the usage interface of StreamHistory the same as Stream Adapter and Extender. by @Readon in #1418
• Update C++ version CFLAGS as Verilator requires C++14 or newer by @saahm in #1428
• [regif] feature upgrade refactoring by @jijingg in #1409
• [regif] #1409 review close by @jijingg in #1434
• inline literal input for some case by @yportne13 in #1437
• Verify component without withAsync option with synchronous reset as default. by @Readon in #1435
• VexiiRiscv branch merge by @Dolu1990 in #1415
• RegIf support Secure TrustZone by @jijingg in #1438
• add missing match case for ElabOrderId.getName by @KireinaHoro in #1444
• Constraint writer for Xilinx Vivado (reopened: CDC rework) by @KireinaHoro in #1369
• [regif] Ram addr width issue fix by @jijingg in #1447

New Contributors

• @AtaraxiaZ made their first contribution in #1332
• @Tectu made their first contribution in #1348
• @jdavidberger made their first contribution in #1352
• @fayalalebrun made their first contribution in #1359
• @march1993 made their first contribution in #1395
• @mrberman87 made their first contribution in #1394
• @louiecaulfield made their first contribution in #1423
• @saahm made their first contribution in #1428

Full Changelog: v1.10.1...v1.10.2

v1.10.1

What's Changed

• Update build.sc dependencies by @KireinaHoro in #1275
• VerilatorBackend now cache improvement by @Dolu1990 in #1272
• PackedBundle Bug Fix by @dokleina in #1271
• Fix comments for trait BitwiseOp by @g0t00 in #1281
• XSim: better Windows support + add xcix IP import by @oletf in #1246
• AXI and AXI-Stream simulation bus masters by @KireinaHoro in #1288
• driveStream on BusSlaveFactory by @KireinaHoro in #1289
• allow CounterFreeRun to take bitCount by @KireinaHoro in #1292
• add setOutputAsReg by @KireinaHoro in #1293
• scala 2.12 is now the default by @Dolu1990 in #1283
• Composable exp by @Dolu1990 in #1297
• Sim test folder by @Dolu1990 in #1279

New Contributors

• @KireinaHoro made their first contribution in #1275
• @g0t00 made their first contribution in #1281
• @oletf made their first contribution in #1246

Full Changelog: v1.10.0...v1.10.1

v1.10.0

This release integrate the new pipelining API (spinal.lib.misc.pipeline) which is documented here :

• https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/introduction.html

What's Changed

• Fix hierarchy violation error for toplevel by @andreasWallner in #1231
• reduce size of the generated verilog for resize/access expressions by @Dolu1990 in #1242
• Merge bus-fabric branch back to dev by @Dolu1990 in #1244
• Add lib.misc.pipeline + lib.misc.plugin API by @Dolu1990 in #1240
• disable scalafmt action by @Dolu1990 in #1243
• pipeline API SignalKey / Connector refractoring by @Dolu1990 in #1250
• Include blackbox sources in formal verification output by @C-Elegans in #1257
• Composable exp PR of doom by @Dolu1990 in #1268
• Idsl moduledef by @Dolu1990 in #1269
• Composable exp by @Dolu1990 in #1270

Full Changelog: v1.9.4...v1.10.0

v1.9.4

What's Changed

• Use simProxy for driving clock by @andreasWallner in #1175
• An experimental PR to use docker image github provided as a CI environment. by @Readon in #1099
• Improve error messages for <> by @andreasWallner in #1186
• Move DDR controller sim to tester to keep it updated. by @Readon in #1189
• Reg Chead mask and shift don't print when field width equal to busdata width by @xiaozhulanshan in #1126
• Fix PackedBundle unpack element bounds filter by @kleinai in #1187
• move tests to speed up ci. by @Readon in #1192
• move tests into core test. by @Readon in #1197
• Bug fix for #1190: VCS run flag not pass to simv by @wswslzp in #1202
• DFI Interface by @LurenAA in #1183
• Add convenience overloads for sleep/forkStimulus by @andreasWallner in #1208
• Add init parameter to Timeout by @andreasWallner in #1207
• Update C++ version for verilator (to C++14) by @andreasWallner in #1210
• Fix signal name typos by @IanBoyanZhang in #1212
• Add option for IO instantitation to InOutWrapper by @andreasWallner in #1215
• Update built Scala minor version to latest by @andreasWallner in #1218
• Bus fabric by @Dolu1990 in #1223
• fix the signedDivider component bugs by @xie-1399 in #1220
• Iconnectable by @xueweiwujxw in #1073
• Added explicit net types to verilog ports by @RiceShelley in #1228
• Fix signal names with $ for verilator by @andreasWallner in #1230

New Contributors

• @LurenAA made their first contribution in #1183
• @IanBoyanZhang made their first contribution in #1212
• @xie-1399 made their first contribution in #1220
• @xueweiwujxw made their first contribution in #1073
• @RiceShelley made their first contribution in #1228

Full Changelog: v1.9.3...v1.9.4

v1.9.3

Mostly 3 important things :

• Fix Apb3CC metastability when empty
• Prevent Verilator from silently exiting the app on $finish (assertion)
• Fix broken scalatic jar dependency giving issues at compilation

Note that Verilator upstream itself may have an issue with clock edges at time 0 :
verilator/verilator#4424

New Contributors

• @ZhaokunHu made their first contribution in #1079
• Generate diagrams based on SpinalHDL code by @ZhaokunHu in #1079

Full Changelog: v1.9.2...v1.9.3

v1.9.2

Mostly fixes, but also add the new "reader" API, see the https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Advanced%20ones/slots.html#slots demo (on the bottom, "reader")

What's Changed

• [regif] AXI-lite4 Rdata BugFix by @jijingg in #1168
• spinal.lib.bus.fabric reusable base classes by @Dolu1990 in #1160

Full Changelog: v1.9.1...v1.9.2

v1.9.0

! This release fix the StreamFifoCC from leaking metastable io.pop.payload when empty !

What's Changed

• Improve formal verification on fifo-rework by @likewise in #1146
• Add tilelink support + many little improvements by @Dolu1990 in #1148
• Fifo rework by @Dolu1990 in #1150
• Fifo rework by @Dolu1990 in #1149
• retide the verification code for StreamTransactionExtender. by @Readon in #1151
• VivadoFlow: Fix issues with getFMax() and getArea(), and improve. by @likewise in #1154
• Fix StreamFifoCC from leaking metastable io.pop.payload when empty by @Dolu1990 in #1167

Full Changelog: v1.8.2...v1.9.0

v1.8.2

What's Changed

• fix check for wide signals by @jonnykl in #1074
• feat(lib): add Stream Unpacker by @dokleina in #814
• PhysicalUnit formatting by @andreasWallner in #1075
• Disable setAffinity on Windows platform by @kazutoiris in #1093
• RegIf update by @jijingg in #1097
• Calculate ice40 pll by @andreasWallner in #1080
• Use element width for PackedBundle width by @kleinai in #1101
• Compile for all supported versions during CI by @andreasWallner in #1102
• Propagate tags from Tristates when using InOutWrapper by @kleinai in #1088
• Packed Word Bundle by @dokleina in #1038
• add explicit unsupported feature error of axi4 downsizer. by @Readon in #1103
• Release docker images for each version while tag is pushing. by @Readon in #1098
• Regif Chead union struct name add prefix by @xiaozhulanshan in #1113
• Scala 2.13 build fixes by @dlmiles in #1114
• Update LICENSE by @Xorlent in #1112
• Deprecate genIf by @andreasWallner in #1118
• feature: add Jtag VPI support for sim by @allexoll in #1095
• Fix HDL names of memory ports by @andreasWallner in #1119
• Make type of register value in CHeaderGenerator configurable by @C-Elegans in #1121
• core: RFC object SmtBmcSolver extends Enumeration: TYPOs ? by @dlmiles in #1120
• Add setAll() and clearAll() for Data by @MarekPikula in #1078
• Rework PackedBundle packing to avoid width confusion by @kleinai in #1124
• Reset AxiLite4Driver on instantiation by @andreasWallner in #1139

New Contributors

• @xiaozhulanshan made their first contribution in #1113
• @dlmiles made their first contribution in #1114
• @Xorlent made their first contribution in #1112

Full Changelog: v1.8.1...v1.8.2

v1.8.1

Finaly out <3

What's Changed

• Fix literal comp range check by @Dolu1990 in #989
• Make APB3CCToggle sensitive to PSEL by @distributed in #990
• publish tester library locally. by @Readon in #992
• #985 Move from @[file row:col] to @ file row by @Dolu1990 in #993
• feat: add comparison operators to PhysicalNumber by @andreasWallner in #997
• feat: add ECP5 EHXPLLL blackbox and some helper functions by @kleinai in #995
• ci: fix missing iverilog error by @numero-744 in #1000
• AxiLite4: Add read only and write only driver classes by @kleinai in #1007
• feat(regif): apb4 support and busif improvment by @jijingg in #976
• fix: fix OS version to ubuntu20 and revert to build iverilog into cache. by @Readon in #1009
• fix: fixes getFanOut; adds test for data analyzer by @wswslzp in #994
• build: upgrade dependency versions by @kleinai in #1016
• ci: cache management + code organization by @numero-744 in #1017
• Axi4: Add extra helper methods by @kleinai in #1023
• ci: fix push-docs by @numero-744 in #1019
• Fix crash when Mem word type is zero bits by @kleinai in #1026
• Implement addRunFlag(), needed by GHDL. by @likewise in #1028
• Naxriscv by @Dolu1990 in #1032
• Add GHDL sim backend support for different waveform formats. by @likewise in #1033
• feat(lib): Axi4 to AxiLite4 conversions by @kleinai in #1002
• fix the missing tester package while publishing locally. by @Readon in #1034
• [regif] resevedAddress default value configable by @jijingg in #1035
• regif parasiteFieldAt method added by @jijingg in #1037
• [regif] fix readData hold issue for the reason of security by @jijingg in #1039
• [Fix] fix typo by @chenbo-again in #1043
• Axis width fixes by @kleinai in #1041
• Fix resized data handling in tuple assignment by @andreasWallner in #1045
• Make SpinalFormalConfig members class parameters by @andreasWallner in #1055
• Fix subdivideIn(..., n bit) for corner cases by @andreasWallner in #1051
• Set the correct reset signal type (polarity) in QSys IP file by @tlupick in #1059
• Retide the generated files by tester/test cases. by @Readon in #1053
• Add testcases for analog connections by @andreasWallner in #1062
• Fix cocotb test cases by @andreasWallner in #1065
• Inout fix by @Dolu1990 in #1046
• [Fix] polish AhbLite3Interconnect example in comment which can not co… by @chenbo-again in #1064

New Contributors

• @chenbo-again made their first contribution in #1043

Full Changelog: v1.8.0...v1.8.1

v1.8.0b

Fix SpinalEnum not being usable outside SpinalHDL context

Full Changelog: v1.8.0a...v1.8.0b