miaou

source/VexiiRiscv/Decode/index.rst

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+Decode
+============
+
+A few plugins operate in the fetch stage : 
+
+- DecodePipelinePlugin
+- AlignerPlugin
+- DecoderPlugin
+- DispatchPlugin
+- DecodePredictionPlugin
+
+
+DecodePipelinePlugin
+-------------------------
+
+Provide the pipeline framework for all the decode related hardware.
+It use the spinal.lib.misc.pipeline API but implement multiple "lanes" in it.
+
+
+AlignerPlugin
+-------------------------
+
+Decode the words froms the fetch pipeline into aligned instructions in the decode pipeline
+
+DecoderPlugin
+-------------------------
+
+Will :
+
+- Decode instruction
+- Generate ilegal instruction exception
+- Generate "interrupt" instruction
+
+DecodePredictionPlugin
+-------------------------
+
+The purpose of this plugin is to ensure that no branch/jump prediction was made for non branch/jump instructions.
+In case this is detected, the plugin will just flush the pipeline and set the fetch PC to redo everything, but this time with a "first prediction skip"
+
+DispatchPlugin
+-------------------------
+
+Will : 
+
+- Collect instruction from the end of the decode pipeline
+- Try to dispatch them ASAP on the multiple "layers" available
+
+Here is a few explenation about execute lanes and layers : 
+
+- A execute lane represent a path toward which an instruction can be executed.
+- A execute lane can have one or many layers, which can be used to implement things as early ALU / late ALU
+- Each layer will have static a scheduling priority
+
+The DispatchPlugin doesn't require lanes or layers to be symetric in any way.
+
+
+
+

source/VexiiRiscv/Execute/index.rst

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+Execute
+============
+
+Many plugins operate in the fetch stage. Some provide infrastructures : 
+
+- ExecutePipelinePlugin
+- ExecuteLanePlugin
+- RegFilePlugin
+- SrcPlugin
+- RsUnsignedPlugin
+- IntFormatPlugin
+- WriteBackPlugin
+- LearnPlugin
+
+Some implement regular instructions 
+
+- IntAluPlugin
+- BarrelShifterPlugin
+- BranchPlugin
+- MulPlugin
+- DivPlugin
+- LsuCachelessPlugin
+
+Some implement CSR, privileges and special instructions
+
+- CsrAccessPlugin
+- CsrRamPlugin
+- PrivilegedPlugin
+- PerformanceCounterPlugin
+- EnvPlugin
+
+
+ExecutePipelinePlugin
+-----------------------
+
+Provide the pipeline framework for all the execute related hardware with the following specificities : 
+
+- It is based on the spinal.lib.misc.pipeline API and can host multiple "lanes" in it.
+- For flow control, the lanes can only freeze the whole pipeline
+- The pipeline do not collapse bubbles (empty stages)
+
+
+ExecuteLanePlugin
+-----------------------
+
+Implement an execution lane in the ExecutePipelinePlugin
+
+RegFilePlugin
+-----------------------
+
+Implement one register file, with the possibility to create new read / write port on demande
+
+SrcPlugin
+-----------------------
+
+Provide some early integer values which can mux between RS1/RS2 and multiple RISC-V instruction's literal values
+
+RsUnsignedPlugin
+-----------------------
+
+Used by mul/div in order to get an unsigned RS1/RS2 value early in the pipeline
+
+IntFormatPlugin
+-----------------------
+
+Alows plugins to write integer values back to the register file through a optional sign extender.
+It uses WriteBackPlugin as value backend.
+
+WriteBackPlugin
+-----------------------
+
+Used by plugins to provide the RD value to write back to the register file
+
+LearnPlugin
+----------------
+
+Will collect all interface which provide jump/branch learning interfaces to aggregate them into a single one, which will then be used by branch prediction plugins to learn.
+
+IntAluPlugin
+-----------------------
+
+Implement the arithmetic, binary and literal instructions (ADD, SUB, AND, OR, LUI, ...)
+
+BarrelShifterPlugin
+-----------------------
+
+Implement the shift instructions in a non-blocking way (no iterations). Fast but "heavy".
+
+BranchPlugin
+-----------------------
+
+Will : 
+
+- Implement branch/jump instruction
+- Correct the PC / History in the case the branch prediction was wrong
+- Provide a learn interface to the LearnPlugin
+
+
+MulPlugin
+-----------------------
+
+- Implement multiplication operation using partial multiplications and then summing their result
+- Done over multiple stage
+- Can optionaly extends the last stage for one cycle in order to buffer the MULH bits
+
+DivPlugin
+-----------------------
+
+- Implement the division/remain 
+- 2 bits per cycle are solved.
+- When it start, it scan for the numerator leading bits for 0, and can skip dividing them (can skip blocks of XLEN/4)
+
+LsuCachelessPlugin
+-----------------------
+
+- Implement load / store through a cacheless memory bus
+- Will fork the cmd as soon as fork stage is valid (with no flush)
+- Handle backpresure by using a little fifo on the response data
+
+CsrAccessPlugin
+-----------------------
+
+- Implement the CSR instruction
+- Provide an API for other plugins to specify its hardware mapping
+
+CsrRamPlugin
+-----------------------
+
+- Implement a shared on chip ram
+- Provide an API which allows to staticaly allocate space on it
+- Provide an API to create read / write ports on it
+- Used by various plugins to store the CSR contents in a FPGA efficient way 
+
+PrivilegedPlugin
+-----------------------
+
+- Implement the RISCV privileged spec
+- Implement the trap buffer / FSM
+- Use the CsrRamPlugin to implement various CSR as MTVAL, MTVEC, MEPC, MSCRATCH, ...
+
+PerformanceCounterPlugin
+-----------------------
+
+- Implement the privileged performance counters in a very FPGA way
+- Use the CsrRamPlugin to store most of the counter bits
+- Use a dedicated 7 bits hardware register per counter
+- Once that 7 bits register MSB is set, a FSM will flush it into the CsrRamPlugin
+
+
+EnvPlugin
+------------------------
+
+- Implement a few instructions as MRET, SRET, ECALL, EBREAK

source/VexiiRiscv/Fetch/index.rst

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+Fetch
+============
+
+A few plugins operate in the fetch stage : 
+
+- FetchPipelinePlugin
+- PcPlugin
+- FetchCachelessPlugin
+- BtbPlugin
+- GSharePlugin
+- HistoryPlugin
+
+FetchPipelinePlugin
+-------------------------
+
+Provide the pipeline framework for all the fetch related hardware. It use the native spinal.lib.misc.pipeline API without any restriction.
+
+PcPlugin
+-------------------------
+
+Will :
+
+- implement the fetch program counter register
+- inject the program counter in the first fetch stage
+- allow other plugin to create "jump" interface allowing to override the PC value
+
+Jump interfaces will impact the PC value injected in the fetch stage in a combinatorial manner to reduce latency.
+
+FetchCachelessPlugin
+-------------------------
+
+Will : 
+
+- Generate a fetch memory bus
+- Connect that memory bus to the fetch pipeline with a response buffer
+- Allow out of order memory bus responses (for maximal compatibility)
+- Always generate aligned memory accesses
+
+
+BtbPlugin
+-------------------------
+
+Will :
+
+- Implement a branch target buffer in the fetch pipeline
+- Implement a return address stack buffer
+- Predict which slices of the fetched word are the last slice of a branch/jump
+- Predict the branch/ĵump target
+- Use the FetchConditionalPrediction plugin (GSharePlugin) to  know if branch should be taken
+- Apply the prediction (flush + pc update + history update)
+- Learn using the LearnPlugin interface
+- Implement "ways" named chunks which are staticaly assigned to groups of word's slices, allowing to predict multiple branch/jump present in the same word
+
+GSharePlugin
+-------------------------
+
+Will : 
+
+- Implement a FetchConditionalPrediction (GShare flavor)
+- Learn using the LearnPlugin interface
+- Will not apply the prediction via flush / pc change, another plugin will do that
+
+HistoryPlugin
+-------------------------
+
+Will : 
+
+- implement the branch history register
+- inject the branch history in the first fetch stage
+- allow other plugin to create interface to override the branch history value (on branch prediction / execution)
+
+branch history interfaces will impact the branch history value injected in the fetch stage in a combinatorial manner to reduce latency.