Update perf

SpinalHDL · Feb 21, 2024 · 9c16c5c · 9c16c5c
1 parent e04dd94
commit 9c16c5c
Show file tree

Hide file tree

Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/source/VexiiRiscv/Introduction/index.rst b/source/VexiiRiscv/Introduction/index.rst
@@ -19,7 +19,7 @@ VexiiRiscv is a from scratch second iteration of VexRiscv, with the following go
 On this date (22/01/2024) the status is : 
 
 - rv 32/64 imacsu supported 
-- Can run baremetal benchmarks (2.46 dhrystone/mhz, 5.13 coremark/mhz)
+- Can run baremetal benchmarks (2.50 dhrystone/mhz, 5.24 coremark/mhz)
 - single/dual issue supported
 - late-alu supported
 - BTB/RAS/GShare branch prediction supported

diff --git a/source/VexiiRiscv/Performance/index.rst b/source/VexiiRiscv/Performance/index.rst
@@ -14,11 +14,11 @@ It is still very early in the developement, but here are some metrics :
 +---------------+----------------+
 | GShare        | 4KB            |
 +---------------+----------------+
-| Dhrystone/MHz | 2.46           |
+| Dhrystone/MHz | 2.50           |
 +---------------+----------------+
-| Coremark/MHz  | 5.13           |
+| Coremark/MHz  | 5.24           |
 +---------------+----------------+
-| EmBench       | 1.59           |
+| EmBench       | 1.62           |
 +---------------+----------------+
 
 It is too early for area / fmax metric, there is a lot of design space exploration to do which will trade IPC against FMax / Area.