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Decode | ||
============ | ||
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A few plugins operate in the fetch stage : | ||
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- DecodePipelinePlugin | ||
- AlignerPlugin | ||
- DecoderPlugin | ||
- DispatchPlugin | ||
- DecodePredictionPlugin | ||
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DecodePipelinePlugin | ||
------------------------- | ||
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Provide the pipeline framework for all the decode related hardware. | ||
It use the spinal.lib.misc.pipeline API but implement multiple "lanes" in it. | ||
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AlignerPlugin | ||
------------------------- | ||
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Decode the words froms the fetch pipeline into aligned instructions in the decode pipeline | ||
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DecoderPlugin | ||
------------------------- | ||
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Will : | ||
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- Decode instruction | ||
- Generate ilegal instruction exception | ||
- Generate "interrupt" instruction | ||
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DecodePredictionPlugin | ||
------------------------- | ||
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The purpose of this plugin is to ensure that no branch/jump prediction was made for non branch/jump instructions. | ||
In case this is detected, the plugin will just flush the pipeline and set the fetch PC to redo everything, but this time with a "first prediction skip" | ||
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DispatchPlugin | ||
------------------------- | ||
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Will : | ||
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- Collect instruction from the end of the decode pipeline | ||
- Try to dispatch them ASAP on the multiple "layers" available | ||
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Here is a few explenation about execute lanes and layers : | ||
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- A execute lane represent a path toward which an instruction can be executed. | ||
- A execute lane can have one or many layers, which can be used to implement things as early ALU / late ALU | ||
- Each layer will have static a scheduling priority | ||
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The DispatchPlugin doesn't require lanes or layers to be symetric in any way. | ||
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Execute | ||
============ | ||
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Many plugins operate in the fetch stage. Some provide infrastructures : | ||
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- ExecutePipelinePlugin | ||
- ExecuteLanePlugin | ||
- RegFilePlugin | ||
- SrcPlugin | ||
- RsUnsignedPlugin | ||
- IntFormatPlugin | ||
- WriteBackPlugin | ||
- LearnPlugin | ||
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Some implement regular instructions | ||
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- IntAluPlugin | ||
- BarrelShifterPlugin | ||
- BranchPlugin | ||
- MulPlugin | ||
- DivPlugin | ||
- LsuCachelessPlugin | ||
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Some implement CSR, privileges and special instructions | ||
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- CsrAccessPlugin | ||
- CsrRamPlugin | ||
- PrivilegedPlugin | ||
- PerformanceCounterPlugin | ||
- EnvPlugin | ||
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ExecutePipelinePlugin | ||
----------------------- | ||
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Provide the pipeline framework for all the execute related hardware with the following specificities : | ||
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- It is based on the spinal.lib.misc.pipeline API and can host multiple "lanes" in it. | ||
- For flow control, the lanes can only freeze the whole pipeline | ||
- The pipeline do not collapse bubbles (empty stages) | ||
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ExecuteLanePlugin | ||
----------------------- | ||
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Implement an execution lane in the ExecutePipelinePlugin | ||
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RegFilePlugin | ||
----------------------- | ||
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Implement one register file, with the possibility to create new read / write port on demande | ||
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SrcPlugin | ||
----------------------- | ||
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Provide some early integer values which can mux between RS1/RS2 and multiple RISC-V instruction's literal values | ||
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RsUnsignedPlugin | ||
----------------------- | ||
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Used by mul/div in order to get an unsigned RS1/RS2 value early in the pipeline | ||
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IntFormatPlugin | ||
----------------------- | ||
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Alows plugins to write integer values back to the register file through a optional sign extender. | ||
It uses WriteBackPlugin as value backend. | ||
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WriteBackPlugin | ||
----------------------- | ||
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Used by plugins to provide the RD value to write back to the register file | ||
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LearnPlugin | ||
---------------- | ||
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Will collect all interface which provide jump/branch learning interfaces to aggregate them into a single one, which will then be used by branch prediction plugins to learn. | ||
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IntAluPlugin | ||
----------------------- | ||
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Implement the arithmetic, binary and literal instructions (ADD, SUB, AND, OR, LUI, ...) | ||
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BarrelShifterPlugin | ||
----------------------- | ||
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Implement the shift instructions in a non-blocking way (no iterations). Fast but "heavy". | ||
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BranchPlugin | ||
----------------------- | ||
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Will : | ||
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- Implement branch/jump instruction | ||
- Correct the PC / History in the case the branch prediction was wrong | ||
- Provide a learn interface to the LearnPlugin | ||
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MulPlugin | ||
----------------------- | ||
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- Implement multiplication operation using partial multiplications and then summing their result | ||
- Done over multiple stage | ||
- Can optionaly extends the last stage for one cycle in order to buffer the MULH bits | ||
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DivPlugin | ||
----------------------- | ||
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- Implement the division/remain | ||
- 2 bits per cycle are solved. | ||
- When it start, it scan for the numerator leading bits for 0, and can skip dividing them (can skip blocks of XLEN/4) | ||
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LsuCachelessPlugin | ||
----------------------- | ||
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- Implement load / store through a cacheless memory bus | ||
- Will fork the cmd as soon as fork stage is valid (with no flush) | ||
- Handle backpresure by using a little fifo on the response data | ||
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CsrAccessPlugin | ||
----------------------- | ||
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- Implement the CSR instruction | ||
- Provide an API for other plugins to specify its hardware mapping | ||
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CsrRamPlugin | ||
----------------------- | ||
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- Implement a shared on chip ram | ||
- Provide an API which allows to staticaly allocate space on it | ||
- Provide an API to create read / write ports on it | ||
- Used by various plugins to store the CSR contents in a FPGA efficient way | ||
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PrivilegedPlugin | ||
----------------------- | ||
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- Implement the RISCV privileged spec | ||
- Implement the trap buffer / FSM | ||
- Use the CsrRamPlugin to implement various CSR as MTVAL, MTVEC, MEPC, MSCRATCH, ... | ||
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PerformanceCounterPlugin | ||
-------------------------------- | ||
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- Implement the privileged performance counters in a very FPGA way | ||
- Use the CsrRamPlugin to store most of the counter bits | ||
- Use a dedicated 7 bits hardware register per counter | ||
- Once that 7 bits register MSB is set, a FSM will flush it into the CsrRamPlugin | ||
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EnvPlugin | ||
------------------------ | ||
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- Implement a few instructions as MRET, SRET, ECALL, EBREAK |
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Fetch | ||
============ | ||
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A few plugins operate in the fetch stage : | ||
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- FetchPipelinePlugin | ||
- PcPlugin | ||
- FetchCachelessPlugin | ||
- BtbPlugin | ||
- GSharePlugin | ||
- HistoryPlugin | ||
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FetchPipelinePlugin | ||
------------------------- | ||
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Provide the pipeline framework for all the fetch related hardware. It use the native spinal.lib.misc.pipeline API without any restriction. | ||
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PcPlugin | ||
------------------------- | ||
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Will : | ||
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- implement the fetch program counter register | ||
- inject the program counter in the first fetch stage | ||
- allow other plugin to create "jump" interface allowing to override the PC value | ||
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Jump interfaces will impact the PC value injected in the fetch stage in a combinatorial manner to reduce latency. | ||
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FetchCachelessPlugin | ||
------------------------- | ||
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Will : | ||
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- Generate a fetch memory bus | ||
- Connect that memory bus to the fetch pipeline with a response buffer | ||
- Allow out of order memory bus responses (for maximal compatibility) | ||
- Always generate aligned memory accesses | ||
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BtbPlugin | ||
------------------------- | ||
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Will : | ||
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- Implement a branch target buffer in the fetch pipeline | ||
- Implement a return address stack buffer | ||
- Predict which slices of the fetched word are the last slice of a branch/jump | ||
- Predict the branch/ĵump target | ||
- Use the FetchConditionalPrediction plugin (GSharePlugin) to know if branch should be taken | ||
- Apply the prediction (flush + pc update + history update) | ||
- Learn using the LearnPlugin interface | ||
- Implement "ways" named chunks which are staticaly assigned to groups of word's slices, allowing to predict multiple branch/jump present in the same word | ||
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GSharePlugin | ||
------------------------- | ||
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Will : | ||
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- Implement a FetchConditionalPrediction (GShare flavor) | ||
- Learn using the LearnPlugin interface | ||
- Will not apply the prediction via flush / pc change, another plugin will do that | ||
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HistoryPlugin | ||
------------------------- | ||
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Will : | ||
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- implement the branch history register | ||
- inject the branch history in the first fetch stage | ||
- allow other plugin to create interface to override the branch history value (on branch prediction / execution) | ||
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branch history interfaces will impact the branch history value injected in the fetch stage in a combinatorial manner to reduce latency. |
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