Update perf

SpinalHDL · Feb 15, 2024 · f27c689 · f27c689
1 parent f3b71a8
commit f27c689
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/source/VexiiRiscv/Introduction/index.rst b/source/VexiiRiscv/Introduction/index.rst
@@ -18,8 +18,8 @@ VexiiRiscv is a from scratch second iteration of VexRiscv, with the following go
 
 On this date (22/01/2024) the status is : 
 
-- rv 32/64 imacsu supported
-- Can run baremetal benchmarks (2.24 dhrystone/mhz, 4.66 coremark/mhz)
+- rv 32/64 imacsu supported 
+- Can run baremetal benchmarks (2.46 dhrystone/mhz, 4.80 coremark/mhz)
 - single/dual issue supported
 - late-alu supported
 - BTB/RAS/GShare branch prediction supported

diff --git a/source/VexiiRiscv/Performance/index.rst b/source/VexiiRiscv/Performance/index.rst
@@ -16,11 +16,11 @@ Note those are done without data cache. A data cache would likely improve the pe
 +---------------+----------------+
 | GShare        | 4KB            |
 +---------------+----------------+
-| Dhrystone/MHz | 2.24           |
+| Dhrystone/MHz | 2.46           |
 +---------------+----------------+
-| Coremark/MHz  | 4.66           |
+| Coremark/MHz  | 4.80           |
 +---------------+----------------+
-| EmBench       | 1.47           |
+| EmBench       | 1.59           |
 +---------------+----------------+
 
 It is too early for area / fmax metric, there is a lot of design space exploration to do which will trade IPC against FMax / Area.