Spv merge to spv 9 #945
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Spv merge to spv 9 #945
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* modify tile i/o delay constraints to speed up inter-tile paths * Update pe and mem to use ptpx for genlibdb instead of innovus * fix sram_pwr.v name in memcore node * Fix error in glc stall i/o delay constraint * set use_local_garnet param to false in full chip so we always use aha master rtl * modify clamp check to accept And gates as well as AO * change to depth 2 fifo in fiber access * Ensure welltaps added AFTER endcaps in power domains flow * Remove branch checkouts in gen_rtl * auto cleanup for tempdir * should be str, not int * Some QOL updates - PE-related * No longer generate PE locally, let conftest take care of it * Remove PE gen from regression * add fifo depth to core combiner * get rid of some prints * Dump several output files * Fix variable i to idx * Fix variable i to idx * Change 0 to idx * path resolve for output dump * Remove unneeded dont_touch constraints from pe and mem * Create common custom-cts node * Add custom-cts node for fullchip * add custom-cts node for glb_top * some cleanup, add dumping gold matrix for aha comparison * hook in height/width * write tensor name * add lvs_adk step to tile array * Remove min/max clk tree path from innovus genlib * Xgcd fixes * Fix pgnet cutlayer blockages in tile array * get rid of unneccessary circuit generation when dealing with pnr only * more robust file extension removal...lol * Add more space between mem tile srams to fit well tap cols * Lower pe density target * Turn off m3 vdd sparsity in pe * turn of m3 vdd sparsity in mem, slide aon over to fit tap cols * move glb clk/reset pins to higher layer * remove spice from xgcd * increase min_delay for glb_tile signals to prevent hold viols in inter-tile paths * Move glb_tile to -fixedGap well tap insertion to prevent drc * Add custom-cts node to glb_tile graph * Ensure that fullchip power node uses fixed gap well tap insertion * Run fill before adding sealring * Revert "Run fill before adding sealring" This reverts commit 52697cc. * more fixed gap well tap insertion in fullchip * skip dumping glb for dense * Disconnect drc-pm from debugcalibre in fc graph * Remove cts routing rules from glb_top, add insertion delay parms to glb_tile pins * Remove old script * Add insertion-delay ccopt property to glb and tile array clk pins in fc * propagate glb_top interface multicycle paths to top level * temporarily false path xgcd in fc * Update feature numbers in pwr-aware tile gls * Remove vcd dump from-pwr-aware gls to speed up * Bring glb design files from spVspV * Add back gf_sram.py * Get rid of CTS NDRs * Don't build glc hierarchically in full chip * LVS BOX for XGCD * use wide-opt buffet for fiber access * Increase full chip hold margin * Updated pond mapping * Added assertions and expanded pond renaming to 2 in/out ports * Updated pond config in design_top * Fixed rom issue * Added packed pes and ponds to netlist_info.txt * Revert "Get rid of CTS NDRs" This reverts commit 64432e2. * Change xgcd spi to lvs.v * Add lvs_adk step in fc graph to lvs can use a different adk view than rest of flow * Fix bug where blockage intended for pg vias blocked pg stripes * Tweak top level halos/placements to get rid of GRBOOL drcs * Revert "Don't build glc hierarchically in full chip" This reverts commit edb0b2d. * increase mem tile hold target * Increase pe density target * Power domains tweaks to prune excess power switches, fix drcs * three level pond swapping done * allow fifo mode for tile .lib files; ensure not empty to break comb paths * Turn off interconnect_only for mem rtl gen to get rid of rtl errors * Add ESD labels to power bumps * propagate glb multicycle paths to top level constraints * increase dist between srams and glb * fix bot/top typos in fc blockage names * obviate need for fault - allows us to run many more verilogZ * Fix VV and T1 via drc errors * Remove xgcd clk constraint, since it's already in .lib, make async with nic clk * Remove rdl ptfm_ctrl to reflect soc change * Add xgcd lvs files * Add xgcd lvs files * fleshing out tb, fix glb bs * hack, but don't create flush port on io core * zero input * Removed try block * Add parameter to control flush register * Change indentation to 4 spaces * Fixing scheduling * use master branch of soc repo * Remove xgcd lvs box * Add target_insertion_delay to pe to try and match mem ins delay * tweak tile array halo to fix drcs * Relax reset and stall constraints in tile array * Space out M3 stripes in tiles to get rid of density errors * Put input delay back on glb_top reset * relax reset/stall constraints to glb and ta in full chip constraints * constraints update * added sram_clk to cgra async group * use_fifo is true for sparse apps * tile array frequency and hold margin * glb clk frequency 1 GHz * Add xgcd ro.lvs.v * full chip drc steps re-org * Space out m3 stripes for full chip flow * add gf-drc-dp step * Add MAS drc to fullchip * do MAS checks at the very end, after DP * Update xgcd clk name * fix glc hold target slack units bug * Add high output delay on strm_start pulse signals in glc * Increase pe area limit for CI to account for new HW * add dac experiments * fix argparser * add input/output port spec to garnet.py * update mapping mode for ub thin * spelling error * oops * add name suffix * add configuration for sram * Spv merge to spv (#934) * creeping toward a common merged master branch * converging on a single branch -- inconsequential bk pipes * restore original mflowgen tests * refined mflowgen test * Removing some comments * Spv merge to spv 1 (#935) * creeping toward a common merged master branch * converging on a single branch -- inconsequential bk pipes * restore original mflowgen tests * conditional pipeline IV: expand number of branch cases * refined mflowgen test * (re)fixing the run_sim scripts * setup-buildkite: merging good changes from both branches * merging gen_rtl * oops not ready for ANAIOPADs yet * added a couple more files from tsmc branch * tsmc portion of clk_gate was wrong for some reason... * should work for both gf and tsmc * if TSMC / elif GF .... * cleaned up a file * changed to match master-dense * streamout is different for tsmc * one branch to rule them all * merging another file * fixing a typo * added configuration dump * Spv merge to spv 2 (#937) * creeping toward a common merged master branch * converging on a single branch -- inconsequential bk pipes * restore original mflowgen tests * conditional pipeline IV: expand number of branch cases * refined mflowgen test * (re)fixing the run_sim scripts * setup-buildkite: merging good changes from both branches * merging gen_rtl * oops not ready for ANAIOPADs yet * added a couple more files from tsmc branch * tsmc portion of clk_gate was wrong for some reason... * should work for both gf and tsmc * if TSMC / elif GF .... * cleaned up a file * changed to match master-dense * streamout is different for tsmc * one branch to rule them all * merging another file * fixing a typo * Merged Tile_Memcore/contruct.py * Merged Tile_PE/contruct.py * merged fullchip construct.py * Merged mflowgen/pad_frame/construct.py * Merged mflowgen/glb_tile/construct.py * tweak mflowgen/full_chip/construct.py to match dense version * common mflowgen/tile_array/construct.py for amber, onyx * common mflowgen/glb_top/construct.py for amber, onyx * common mflowgen/global_controller/construct.py for amber, onyx * undid an error * undid an(other?) error * final tweak on fc/construct.py -- this one passed full build * added a check to early-out TSMC build failures * buildkite pipeline tweaks * updated vs. latest garnet.py from spVspV branch * Spv merge to spv 3 (#938) * creeping toward a common merged master branch * restore original mflowgen tests * conditional pipeline IV: expand number of branch cases * (re)fixing the run_sim scripts * setup-buildkite: merging good changes from both branches * merging gen_rtl * oops not reday for ANAIOPADs yet * tsmc portion of clk_gate was wrong for some reason... * if TSMC / elif GF .... * streamout is different for tsmc * Merged Tile_Memcore/contruct.py * Merged Tile_PE/contruct.py * merged fullchip construct.py * Merged mflowgen/pad_frame/construct.py * Merged mflowgen/glb_tile/construct.py * tweak mflowgen/full_chip/construct.py to match dense version * common mflowgen/tile_array/construct.py for amber, onyx * common mflowgen/glb_top/construct.py for amber, onyx * common mflowgen/global_controller/construct.py for amber, onyx * final tweak on fc/construct.py -- this one passed full build * added a check to early-out TSMC build failures * updated vs. latest garnet.py from spVspV branch * emergency(?) fix for CI * try again with previously-merged rtl-only pipeline * merged latest set of files from $smd * Now comply with multiple seeds * use matrix tmp dir * safer logic * Spv merge to spv 5 (#939) * creeping toward a common merged master branch * converging on a single branch -- inconsequential bk pipes * restore original mflowgen tests * conditional pipeline IV: expand number of branch cases * refined mflowgen test * (re)fixing the run_sim scripts * setup-buildkite: merging good changes from both branches * merging gen_rtl * oops not ready for ANAIOPADs yet * tsmc portion of clk_gate was wrong for some reason... * if TSMC / elif GF .... * streamout is different for tsmc * Merged Tile_Memcore/contruct.py * Merged Tile_PE/contruct.py * merged fullchip construct.py * Merged mflowgen/pad_frame/construct.py * Merged mflowgen/glb_tile/construct.py * tweak mflowgen/full_chip/construct.py to match dense version * common mflowgen/tile_array/construct.py for amber, onyx * common mflowgen/glb_top/construct.py for amber, onyx * common mflowgen/global_controller/construct.py for amber, onyx * final tweak on fc/construct.py -- this one passed full build * added a check to early-out TSMC build failures * buildkite pipeline tweaks * updated vs. latest garnet.py from spVspV branch * emergency(?) fix for CI * try the previously-passing version of rtl_only.yml * try again with previously-merged rtl-only pipeline * final merge-tweak of this stupid file * merged latest set of files from $smd * gf/tsmc merge of GLB sim files * final tweaks on global_buffer_parameter.py * unified amber/onyx global_buffer.py * unified amber/onyx gen_global_buffer_rdl.py * merged design/glb_addr_gen.py * merged glb_header.py * another glb_header.py merge * merged glb_cfg.py * (re)merge glb_bank_sram_gen.py * merged glb_loop_iter.py * new design_amber dir for amber compatibility * use design_amber for global_buffer.py diffs instead of if-then-else * merge final few GLB files w/dense version(s) * last minute fix to improper code * some small updates * allow give_tensor across many tensors * move verilog generation up * unfortunate * logic bug in script * finally unify the codepath for creating cgra * fixed group size bug and moved reg_write file placement * removed prints * make spVspV work with aha-flow again (#940) * Spv merge to spv 6 (#941) * creeping toward a common merged master branch * converging on a single branch -- inconsequential bk pipes * restore original mflowgen tests * conditional pipeline IV: expand number of branch cases * refined mflowgen test * (re)fixing the run_sim scripts * setup-buildkite: merging good changes from both branches * merging gen_rtl * oops not reday for ANAIOPADs yet * added a couple more files from tsmc branch * tsmc portion of clk_gate was wrong for some reason... * should work for both gf and tsmc * if TSMC / elif GF .... * changed to match master-dense * streamout is different for tsmc * Merged Tile_Memcore/contruct.py * Merged Tile_PE/contruct.py * merged fullchip construct.py * Merged mflowgen/pad_frame/construct.py * Merged mflowgen/glb_tile/construct.py * tweak mflowgen/full_chip/construct.py to match dense version * common mflowgen/tile_array/construct.py for amber, onyx * common mflowgen/glb_top/construct.py for amber, onyx * common mflowgen/global_controller/construct.py for amber, onyx * final tweak on fc/construct.py -- this one passed full build * added a check to early-out TSMC build failures * buildkite pipeline tweaks * updated vs. latest garnet.py from spVspV branch * emergency(?) fix for CI * try the previously-passing version of rtl_only.yml * try with local garnet * fixed a thing maybe * try again with previously-merged rtl-only pipeline * final merge-tweak of this stupid file * merged latest set of files from $smd * gf/tsmc merge of GLB sim files * final tweaks on global_buffer_parameter.py * unified amber/onyx global_buffer.py * unified amber/onyx gen_global_buffer_rdl.py * merged design/glb_addr_gen.py * merged glb_header.py * another glb_header.py merge * merged glb_cfg.py * (re)merge glb_bank_sram_gen.py * merged glb_loop_iter.py * new design_amber dir for amber compatibility * use design_amber for global_buffer.py diffs instead of if-then-else * merge final few GLB files w/dense version(s) * last minute fix to improper code * onyx/amber merge of nic400 files * onyx/amber merge of GLC files * Issue warning if cannot git pull tsmc16 adk * proper shape files * Spv merge to spv 7a (#943) * creeping toward a common merged master branch * conditional pipeline IV: expand number of branch cases * refined mflowgen test * (re)fixing the run_sim scripts * setup-buildkite: merging good changes from both branches * merging gen_rtl * oops not reday for ANAIOPADs yet * added a couple more files from tsmc branch * tsmc portion of clk_gate was wrong for some reason... * should work for both gf and tsmc * if TSMC / elif GF .... * changed to match master-dense * streamout is different for tsmc * one branch to rule them all * Merged Tile_Memcore/construct.py * Merged Tile_PE/construct.py * merged fullchip construct.py * Merged mflowgen/pad_frame/construct.py * Merged mflowgen/glb_tile/construct.py * tweak mflowgen/full_chip/construct.py to match dense version * common mflowgen/tile_array/construct.py for amber, onyx * common mflowgen/glb_top/construct.py for amber, onyx * common mflowgen/global_controller/construct.py for amber, onyx * undid an error * undid an(other?) error * final tweak on fc/construct.py -- this one passed full build * added a check to early-out TSMC build failures * buildkite pipeline tweaks * updated vs. latest garnet.py from spVspV branch * emergency(?) fix for CI * try the previously-passing version of rtl_only.yml * try with local garnet * try again with previously-merged rtl-only pipeline * final merge-tweak of this stupid file * merged latest set of files from $smd * gf/tsmc merge of GLB sim files * final tweaks on global_buffer_parameter.py * unified amber/onyx global_buffer.py * unified amber/onyx gen_global_buffer_rdl.py * merged design/glb_addr_gen.py * merged glb_header.py * another glb_header.py merge * merged glb_cfg.py * (re)merge glb_bank_sram_gen.py * merged glb_loop_iter.py * new design_amber dir for amber compatibility * use design_amber for global_buffer.py diffs instead of if-then-else * merge final few GLB files w/dense version(s) * last minute fix to improper code * onyx/amber merge of nic400 files * onyx/amber merge of GLC files * Issue warning if cannot git pull tsmc16 adk * full_chip constraints merge part 1: constraints_amber * full_chip constraints merge part 2: construct.py continues to use constraints as before * update for new file formats * add 500 offset for glb * Increasing length of timeout for longer resnet layers and adding human sorting for kalhan * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * Spv merge to spv 8 (#944) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * Performance update for aha flow, will merge PR for aha flow when regression finishes * Added printing of some port remapping * merged all sms9 changes from $smd * build_tb with tensor4_multiply2 * fix mode map stuff for MG matrices (hacky?), fix tensor4_multiply2 * tensor4_multiply, tensor4_multiply2, tensor3_linear_multiply passing fabric test * add perf debug * adopted peakrdl fix * sped up aha glb by simplyfing timescale (needs special case for gate level sims) and making waveform flags optional * fix systemrdl bug * merge amber pd power script dirs * merged a power script * updated construct.py scripts to use merged power scripts * Spv merge to spv 9 (#945) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * merged all sms9 changes from $smd * Fix peakrdl html bug --------- Co-authored-by: jack-melchert <56329001+jack-melchert@users.noreply.github.com> * Spv merge to spv 10 (#946) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * merged all sms9 changes from $smd * adopted peakrdl fix * merge amber pd power script dirs * merged a power script * updated construct.py scripts to use merged power scripts * merged mflowgen/common/pwr-aware-gls/assign-pdcr-address.sh from dense repo * merged mflowgen/common/pwr-aware-gls/tb_Tile_*.v * merged gen_sram_macro scripts * debuggin * debuggin FOO2 * fixed missing directory * adopted smd version of streamout_no_uniquify.py (not used by onyx) * cleanup merge w smd * sms11 (final) round 3b * huh maybe onyx CI should not set WHICH_SOC=amber * Fixed typo in run_sim script * working on sparse tiles * fixed a mismanaged verilog testbench for pwr-aware-gls * fixed bug in gtile construct.py * git merge smd12 (full_chip) * git merge smd12 (glb_tile) * git merge smd12 (glb_top) * Spv merge to spv 11 (#947) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * merged all sms9 changes from $smd * adopted peakrdl fix * merge amber pd power script dirs * merged a power script * updated construct.py scripts to use merged power scripts * merged mflowgen/common/pwr-aware-gls/assign-pdcr-address.sh from dense repo * merged mflowgen/common/pwr-aware-gls/tb_Tile_*.v * merged gen_sram_macro scripts * debuggin * fixed missing directory * adopted smd version of streamout_no_uniquify.py (not used by onyx) * cleanup merge w smd * sms11 (final) round 3b * huh maybe onyx CI should not set WHICH_SOC=amber * Fixed typo in run_sim script * fixed a mismanaged verilog testbench for pwr-aware-gls * fixed bug in gtile construct.py * delete old/unused files * merged mflowgen/bin/setup-buildkite.sh * alt amber versions for tile_array/custom-{init,lvs-rules} * merged four files * merged global_buffer/io_placement.py * added tile_array/custom*-amber directories * forgot "import os" * missed a effing curly brace * Spv merge to spv 12 (#948) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * merged all sms9 changes from $smd * adopted peakrdl fix * merge amber pd power script dirs * merged a power script * updated construct.py scripts to use merged power scripts * merged mflowgen/common/pwr-aware-gls/assign-pdcr-address.sh from dense repo * merged mflowgen/common/pwr-aware-gls/tb_Tile_*.v * merged gen_sram_macro scripts * debuggin * fixed missing directory * adopted smd version of streamout_no_uniquify.py (not used by onyx) * cleanup merge w smd * sms11 (final) round 3b * huh maybe onyx CI should not set WHICH_SOC=amber * Fixed typo in run_sim script * fixed a mismanaged verilog testbench for pwr-aware-gls * fixed bug in gtile construct.py * git merge smd12 (full_chip) * git merge smd12 (glb_tile) * git merge smd12 (glb_top) * sms14: merged TOP/cgra/ files * made separate amber version for garnet.py * separate dir for amber headers * same requirements.txt for both amber and onyx versions * slight improvement for pmg.yml test * made separate mapper_amber directory * sms14: unified tests/test_app/Makefile * made separate passes_amber directory * Spv merge to spv 13 (#949) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * merged all sms9 changes from $smd * adopted peakrdl fix * merge amber pd power script dirs * merged a power script * updated construct.py scripts to use merged power scripts * merged mflowgen/common/pwr-aware-gls/assign-pdcr-address.sh from dense repo * merged mflowgen/common/pwr-aware-gls/tb_Tile_*.v * merged gen_sram_macro scripts * debuggin * fixed missing directory * adopted smd version of streamout_no_uniquify.py (not used by onyx) * cleanup merge w smd * sms11 (final) round 3b * huh maybe onyx CI should not set WHICH_SOC=amber * Fixed typo in run_sim script * fixed a mismanaged verilog testbench for pwr-aware-gls * fixed bug in gtile construct.py * git merge smd12 (full_chip) * git merge smd12 (glb_tile) * git merge smd12 (glb_top) * delete old/unused files * merged mflowgen/bin/setup-buildkite.sh * alt amber versions for tile_array/custom-{init,lvs-rules} * merged four files * merged global_buffer/io_placement.py * added tile_array/custom*-amber directories * forgot "import os" * missed a effing curly brace * added tile generation scripts * Added a comment * sync w/amber version: buildkite "glb_top.yml" script * sync w/amber version: buildkite "rtl_only.yml" script * try for a separate conftest_amber.py, see how it goes... * scripts for large sparse matrices * Spv merge to spv 14 (#950) * unified get_tile_array_outputs.sh vs. smd * final (corrected) merge of smd=>sms8 * fixed scoping bug in memtile_util.py * merged all sms9 changes from $smd * adopted peakrdl fix * merge amber pd power script dirs * merged a power script * updated construct.py scripts to use merged power scripts * merged mflowgen/common/pwr-aware-gls/assign-pdcr-address.sh from dense repo * merged mflowgen/common/pwr-aware-gls/tb_Tile_*.v * merged gen_sram_macro scripts * debuggin * fixed missing directory * adopted smd version of streamout_no_uniquify.py (not used by onyx) * cleanup merge w smd * sms11 (final) round 3b * huh maybe onyx CI should not set WHICH_SOC=amber * Fixed typo in run_sim script * fixed a mismanaged verilog testbench for pwr-aware-gls * fixed bug in gtile construct.py * git merge smd12 (full_chip) * git merge smd12 (glb_tile) * git merge smd12 (glb_top) * delete old/unused files * merged mflowgen/bin/setup-buildkite.sh * alt amber versions for tile_array/custom-{init,lvs-rules} * merged four files * merged global_buffer/io_placement.py * added tile_array/custom*-amber directories * forgot "import os" * missed a effing curly brace * sms14: merged TOP/cgra/ files * made separate amber version for garnet.py * separate dir for amber headers * same requirements.txt for both amber and onyx versions * slight improvement for pmg.yml test * made separate mapper_amber directory * sms14: unified tests/test_app/Makefile * made separate passes_amber directory * reset pmg.yml to run all three tile tests again * remove torch * fix glb collat generation * missed file on previous commit * temp fix for bug where route isnt counted for dpr * Fix pytest (#952) * try new pytest maybe * confused container and image * disable requirements.txt-based workflow test * must run pytest from garnet dir, duh * activate correct python environment maybe * install required package pytest-cov * first step toward eliminating bad pytests * wrong syntax for pytest skip * skip failing pond pytests * skip final two failing tests, all remaining tests should pass now * final cleanup maybe * trying out a new ci.yml for aha-flow regressions * struggling with buildkite pipeline syntax :( * agent-specification troubles * ./garnet => . * resnet_tests => pr * image-prune experiments * image-prune experiments -- prune containers as well II * ci.yml final form maybe * An attempt at deprecating requirements.txt in favor of pre-built docker * Delete generic_memory.txt Shouldn't be in the repo...accidentally pushed. * Delete generic_memory_0.txt Shouldn't be in the repo...accidentally pushed. * Delete generic_memory_1.txt Shouldn't be in the repo...accidentally pushed. * Delete generic_memory_2.txt Shouldn't be in the repo...accidentally pushed. --------- Co-authored-by: Alex Carsello <ajcars@stanford.edu> Co-authored-by: mbstrange2 <mstrange@stanford.edu> Co-authored-by: root <kkoul@stanford.edu> Co-authored-by: Taeyoung Kong <kongty@stanford.edu> Co-authored-by: root <melchert@stanford.edu> Co-authored-by: root <kalhankoul96@gmail.com> Co-authored-by: Jake Ke <jackieke724@hotmail.com> Co-authored-by: Gedeon Nyengele <thenextged@gmail.com> Co-authored-by: jack-melchert <56329001+jack-melchert@users.noreply.github.com> Co-authored-by: Po-Han <pohan@stanford.edu> Co-authored-by: root <gina7484@gmail.com> Co-authored-by: Max Strange <46541870+mbstrange2@users.noreply.github.com>
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This pull is 9th in a series that so far includes #934 , #935 , #937 , #938 , #939 , #941 , #943 ,
#944 , slowly merging gf/onyx and tsmc/amber versions back into one, for a single common master branch.
After the most recent pull #944 , the two branches had 84 files difference between them. This pull cuts that down to 74:
Below is a summary of the changes included in this pull, along with an explanation of why each change should have no adverse impact on existing spVspV functionality.
if AMBER then {} else {}clausesedge-blockagesscripts were replaced with symlinks to a single common location, to match what onyx does.custom-lvs-rules-amberfor amber LVS rules, leaving the onyx rules and directory as the default, andconstruct.pywas updated to contextually choose the correct rule-set.These changes have been vetted and have passed both amber full-chip build and onyx aha-flow CI tests.