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bad bpd
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@Bohan-hu
Bohan-hu committed Aug 3, 2020
1 parent d04063a commit 22c2f4d
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Showing 13 changed files with 483 additions and 64 deletions.
319 changes: 319 additions & 0 deletions source/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci
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8 changes: 8 additions & 0 deletions source/sources_1/new/Commit.sv
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Expand Up @@ -206,6 +206,14 @@ module Commit(
end
end

always_comb begin
backend_bpd.updValid <= inst0Good && rob_commit.uOP0.branchType != typeNormal && rob_commit.uOP0.branchType != typeJ;
backend_bpd.updTarget <= rob_commit.uOP0.pc;
backend_bpd.updInfo <= rob_commit.uOP0.predInfo;
backend_bpd.updMisPred <= rob_commit.uOP0.branchTaken != rob_commit.uOP0.predTaken;
backend_bpd.updTaken <= rob_commit.uOP0.branchTaken;
end

always_comb begin
ctrl_commit.flushReq = `FALSE;
backend_if0.redirect = `FALSE;
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1 change: 1 addition & 0 deletions source/sources_1/new/MyCPU.sv
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Expand Up @@ -94,6 +94,7 @@ module mycpu_top(
Ctrl ctrl_if0_1_regs();
Ctrl ctrl_if2_3_regs();
Ctrl ctrl_iCache();
Ctrl ctrl_tage();
Ctrl ctrl_if3();
Ctrl ctrl_if3_output_regs();
Ctrl ctrl_instBuffer();
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1 change: 1 addition & 0 deletions source/sources_1/new/decode.sv
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Expand Up @@ -48,6 +48,7 @@ module decode(
uOP0.pc = inst.pc;
uOP0.predTaken = inst.predTaken;
uOP0.predAddr = inst.predAddr;
uOP0.predInfo = inst.bpdInfo;
uOP0.isDS = inst.isDs;
uOP0.committed = `FALSE;
uOP1.pc = inst.pc;
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33 changes: 17 additions & 16 deletions source/sources_1/new/defines/defines.svh
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Expand Up @@ -265,6 +265,23 @@ typedef logic [5:0] ARFNum; // 逻辑寄存器编号(共34个)
`define NOP_U 8'b01000010
`define WAIT_U 8'b01000101

typedef logic [9:0] TAGEIndex;
typedef logic [2:0] TAGECtr;
typedef logic [7:0] TAGETag;
typedef logic [1:0] TAGEUseful;

typedef struct packed {
logic hit; // 预测命中
TAGEIndex hit_index; // 预测的index，以防历史记录改变
TAGEIndex on_mispred_index; // 预测错误时，要分配的新项的index
logic [1:0] on_mispred_bank; // 预测错误时，需要分配哪个Bank
TAGETag hit_tag; // 命中的Tag
TAGETag on_mispred_tag; // 错误预测时，更新的新项的Tag
logic has_free_to_alloc; // 预测错误时，有新项可以分配
TAGECtr ctr; // 三位饱和计数器
logic [1:0] provider; //
logic has_alter;
} TAGEPred;

typedef struct packed {
logic [31:0] inst;
Expand Down Expand Up @@ -544,23 +561,7 @@ typedef struct packed {
// TODO
} UOPBundle;

typedef logic [9:0] TAGEIndex;
typedef logic [2:0] TAGECtr;
typedef logic [7:0] TAGETag;
typedef logic [1:0] TAGEUseful;

typedef struct packed {
logic hit; // 预测命中
TAGEIndex hit_index; // 预测的index，以防历史记录改变
TAGEIndex on_mispred_index; // 预测错误时，要分配的新项的index
logic [1:0] on_mispred_bank; // 预测错误时，需要分配哪个Bank
TAGETag hit_tag; // 命中的Tag
TAGETag on_mispred_tag; // 错误预测时，更新的新项的Tag
logic has_free_to_alloc; // 预测错误时，有新项可以分配
TAGECtr ctr; // 三位饱和计数器
logic [1:0] provider; //
logic has_alter;
} TAGEPred;

interface Ctrl;
logic pauseReq;
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7 changes: 5 additions & 2 deletions source/sources_1/new/ifu/CtrlUnit.sv
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Expand Up @@ -10,7 +10,8 @@ module CtrlUnit(
Ctrl.master ctrl_iCache,
Ctrl.master ctrl_if3,
Ctrl.master ctrl_if3_output_regs,
Ctrl.master ctrl_instBuffer
Ctrl.master ctrl_instBuffer,
Ctrl.master ctrl_tage
);

logic delayIF3Flush, if3Flush;
Expand All @@ -19,14 +20,16 @@ module CtrlUnit(
assign if3Flush = delayIF3Flush || ctrl_if3.flushReq;


assign ctrl_if0_1_regs.pause = ctrl_instBuffer.pauseReq ||ctrl_iCache.pauseReq;
assign ctrl_if0_1_regs.pause = ctrl_instBuffer.pauseReq || ctrl_iCache.pauseReq;
assign ctrl_if2_3_regs.pause = ctrl_instBuffer.pauseReq;
assign ctrl_iCache.pause = ctrl_instBuffer.pauseReq;
assign ctrl_tage.pause = ctrl_instBuffer.pauseReq || ctrl_iCache.pauseReq;
assign ctrl_if3.pause = ctrl_instBuffer.pauseReq;
assign ctrl_if3_output_regs.pause = ctrl_instBuffer.pauseReq;

assign ctrl_if0_1_regs.flush = `FALSE; //backend_ctrl.flush || ctrl_if3.flushReq;
assign ctrl_iCache.flush = backend_ctrl.flush || ctrl_if3.flushReq;
assign ctrl_tage.flush = backend_ctrl.flush;
assign ctrl_if2_3_regs.flush = backend_ctrl.flush || ctrl_if3.flushReq;
assign ctrl_if3.flush = backend_ctrl.flush;
assign ctrl_if3_output_regs.flush = backend_ctrl.flush;
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26 changes: 25 additions & 1 deletion source/sources_1/new/ifu/IFU.sv
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Expand Up @@ -14,7 +14,7 @@ module IFU(
Ctrl ctrl_if3,
Ctrl ctrl_if3_output_regs,
Ctrl ctrl_nlp,

Ctrl ctrl_tage,
ICache_TLB iCache_tlb,
BackendRedirect backend_if0,
BPDUpdate backend_bpd,
Expand Down Expand Up @@ -48,5 +48,29 @@ module IFU(
IF2_3_reg if23reg(.*);
IF_3 if3(.*);
IF3_Output_reg if3OutputReg(.*);
logic IF3_isBranch, IF3_isJ;
wire [31:0] pred_target;
wire pred_valid, pred_taken;
TAGEPred pred_info;
TAGE u_TAGE(
.clk (clk ),
.rst (rst ),
.pause (ctrl_tage.pause ),
.recover (ctrl_tage.flush ),
.IF3_isBranch (IF3_isBranch ),
.IF3_isJ (IF3_isJ ),
.br_pc (regs_iCache.PC ),
// 送出的结果
.pred_valid (pred_valid ),
.pred_taken (pred_taken ),
.pred_target (pred_target ),
.pred_info (pred_info ),
// 从commit阶段来的
.commit_valid (backend_bpd.updValid ),
.committed_target (backend_bpd.updTarget ),
.committed_pred_info (backend_bpd.updInfo ),
.committed_branch_taken (backend_bpd.updTaken ),
.committed_mispred (backend_bpd.updMisPred )
);

endmodule
32 changes: 28 additions & 4 deletions source/sources_1/new/ifu/IF_3.sv
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Expand Up @@ -16,7 +16,9 @@ module IF_3(
input wire pred_valid, // from bpd
input wire pred_taken, // from bpd
input wire [31:0] pred_target,
input TAGEPred pred_info
input TAGEPred pred_info,
output IF3_isBranch, // To BPD, update the global history
output IF3_isJ
);
logic inst0Jr;
logic inst1Jr;
Expand All @@ -36,7 +38,12 @@ module IF_3(

logic waitDS, lastWaitDS;
logic [31:0] waitDSRedirectTarget;

wire isJ, isBranch;
assign isBranch = inst0Jr | inst0J | inst0Br |
inst1Jr | inst1J | inst1Br ;
assign isJ = inst0J | inst1J ;
assign IF3_isBranch = isBranch;
assign IF3_isJ = isJ;
Predecoder pre0(
.pc (regs_if3.inst0.pc ),
.inst (regs_if3.inst0.inst ),
Expand Down Expand Up @@ -101,6 +108,12 @@ module IF_3(
if(pred_valid) begin
if3_regs.inst0.predTaken = pred_taken;
if3_regs.inst0.predAddr = decodeTarget0;
end else if(if3_regs.inst0.nlpInfo.valid) begin
if3_regs.inst0.predTaken = inst0NLPTaken;
if3_regs.inst0.predAddr = decodeTarget0;
end else begin
if3_regs.inst0.predTaken = `FALSE;
if3_regs.inst0.predAddr = decodeTarget0;
end
end

Expand All @@ -123,6 +136,17 @@ module IF_3(
if3_regs.inst1.predTaken = `TRUE;
if3_regs.inst1.predAddr = decodeTarget1;
end
end else begin
if(pred_valid) begin
if3_regs.inst1.predTaken = pred_taken;
if3_regs.inst1.predAddr = decodeTarget1;
end else if(if3_regs.inst1.nlpInfo.valid) begin
if3_regs.inst1.predTaken = inst1NLPTaken;
if3_regs.inst1.predAddr = decodeTarget1;
end else begin
if3_regs.inst1.predTaken = `FALSE;
if3_regs.inst1.predAddr = decodeTarget1;
end
end

// redirect control
Expand Down Expand Up @@ -204,13 +228,13 @@ module IF_3(
// nlp update info
always_comb begin
if3_nlp.update = 0;
if(if3_regs.inst0.valid && (if3_regs.inst0.bpdInfo.valid || (if3_regs.inst0.isJ && (!inst0Jr || (inst0Jr && if3_regs.inst0.nlpInfo.valid))))) begin
if(if3_regs.inst0.valid && (pred_valid && inst0IsCtrl || (if3_regs.inst0.isJ && (!inst0Jr || (inst0Jr && if3_regs.inst0.nlpInfo.valid))))) begin
if3_nlp.update.pc = if3_regs.inst0.pc;
if3_nlp.update.target = if3_regs.inst0.predAddr;
if3_nlp.update.bimState = if3_regs.inst0.nlpInfo.valid ? if3_regs.inst0.nlpInfo.bimState : 2'b01;
if3_nlp.update.shouldTake = if3_regs.inst0.predTaken;
if3_nlp.update.valid = `TRUE;
end else if(if3_regs.inst1.valid && (if3_regs.inst1.bpdInfo.valid || (if3_regs.inst1.isJ && (!inst1Jr || (inst1Jr && if3_regs.inst1.nlpInfo.valid))))) begin
end else if(if3_regs.inst1.valid && (pred_valid && inst1IsCtrl || (if3_regs.inst1.isJ && (!inst1Jr || (inst1Jr && if3_regs.inst1.nlpInfo.valid))))) begin
if3_nlp.update.pc = if3_regs.inst1.pc;
if3_nlp.update.target = if3_regs.inst1.predAddr;
if3_nlp.update.bimState = if3_regs.inst1.nlpInfo.valid ? if3_regs.inst1.nlpInfo.bimState : 2'b01;
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21 changes: 15 additions & 6 deletions source/sources_1/new/ifu/TAGE.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,9 @@ module TAGE(
input rst,
input pause,
input recover,
input new_branch_happen,
input new_branch_taken,
input IF3_isBranch,
input IF3_isJ,
// input new_branch_taken,
// For branch prediction
input [31:0] br_pc,
output pred_valid,
Expand All @@ -19,23 +20,25 @@ module TAGE(
output TAGEPred pred_info,
// For branch prediction update
input commit_valid,
input [31:0] committed_pc,
input [31:0] committed_target,
input TAGEPred committed_pred_info,
input committed_branch_taken,
input committed_mispred
);

assign pred_target = 0;
TAGEIndex [3:0] index_01;
TAGETag [3:0] PCTags_01;
TAGEIndex [3:0] index_01_r;
TAGETag [3:0] PCTags_01_r;
wire new_branch_taken;
assign new_branch_taken = pred_taken || (IF3_isBranch && IF3_isJ);
wire flush_ubits_hi_01, flush_ubits_lo_01;
TAGE_Phase0 phase0(
.clk(clk),
.rst(rst),
.pause(pause),
.recover(recover),
.new_branch_happen(new_branch_happen),
.new_branch_happen(IF3_isBranch),
.new_branch_taken(new_branch_taken),
.br_pc(br_pc),
.commit_valid(commit_valid),
Expand Down Expand Up @@ -65,17 +68,20 @@ module TAGE(
// Phase 1/2 Regs
TAGEPred TAGEResp_o, TAGEResp_r;
wire PredTaken_o;
wire pred_valid_o;
reg pred_valid_r;
reg PredTaken_r;
TAGE_Phase1 phase1(
.clk(clk),
.rst(rst),
.pause(pause),
.recover(recover),
.PredValid(pred_valid_o),
// 是否需要Flush Useful Bit
.flush_ubits_hi(flush_ubits_hi_01),
.flush_ubits_lo(flush_ubits_lo_01),
// 访问Tage的四个Index
.indexes(index_01_r),
.indexes(index_01),
// For branch prediction
.PCTags(PCTags_01_r),
.TAGEResp(TAGEResp_o),
Expand All @@ -92,12 +98,15 @@ module TAGE(
if(rst) begin
TAGEResp_r <= 0;
PredTaken_r <= 0;
pred_valid_r <= 0;
end else begin
TAGEResp_r <= TAGEResp_o;
PredTaken_r <= PredTaken_o;
pred_valid_r <= pred_valid;
end
end

assign pred_taken = PredTaken_r;
assign pred_info = TAGEResp_r;
assign pred_valid = pred_valid_r;
endmodule
2 changes: 1 addition & 1 deletion source/sources_1/new/ifu/TAGE_Phase0.sv
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Expand Up @@ -26,8 +26,8 @@ module TAGE_Phase0(

wire [9:0] folded_hist_10;
wire [9:0] folded_hist_20;
wire [9:0] folded_hist_30;
wire [9:0] folded_hist_40;
wire [9:0] folded_hist_80;

// Predict Phase 0: Index generation logic

Expand Down
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