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fix axi
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@willson0v0
willson0v0 committed Aug 3, 2020
1 parent 502a5d5 commit 2dc4a2b
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Showing 7 changed files with 88 additions and 33 deletions.
10 changes: 10 additions & 0 deletions source/sources_1/ip/tag_ram/tag_ram.xci
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Expand Up @@ -295,11 +295,21 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_A_Write_Rate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
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6 changes: 3 additions & 3 deletions source/sources_1/new/CP0.sv
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Expand Up @@ -24,9 +24,9 @@ module CP0(
logic [31:0] Count;
logic [31:0] EntryHi;
logic [31:0] Compare;
(* mark_debug = "yes" *)logic [31:0] Status;
(* mark_debug = "yes" *)logic [31:0] Cause;
(* mark_debug = "yes" *)logic [31:0] EPc;
logic [31:0] Status;
logic [31:0] Cause;
logic [31:0] EPc;
logic [31:0] PRId;
logic [31:0] EBase;
logic [31:0] Config;
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2 changes: 1 addition & 1 deletion source/sources_1/new/Commit.sv
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Expand Up @@ -262,5 +262,5 @@ module Commit(
assign exceInfo.interrupt = ext_interrupt_signal;

wire debug_is_branch = rob_commit.uOP0.branchType != typeNormal && inst0Good;
(* mark_debug = "yes" *)wire debug_redirect = backend_if0.redirect;
wire debug_redirect = backend_if0.redirect;
endmodule
38 changes: 19 additions & 19 deletions source/sources_1/new/MyCPU.sv
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Expand Up @@ -8,45 +8,45 @@ module mycpu_top(
input [5:0] ext_int,

output wire [ 3:0] awid ,
output wire [31:0] awaddr ,
output wire [ 7:0] awlen ,
output wire [ 2:0] awsize ,
(* mark_debug = "yes" *)output wire [31:0] awaddr ,
(* mark_debug = "yes" *)output wire [ 3:0] awlen ,
(* mark_debug = "yes" *)output wire [ 2:0] awsize ,
output wire [ 1:0] awburst ,
output wire [ 1:0] awlock ,
output wire [ 3:0] awcache ,
output wire [ 2:0] awprot ,
output wire awvalid ,
input wire awready ,
(* mark_debug = "yes" *)output wire awvalid ,
(* mark_debug = "yes" *)input wire awready ,

output wire [ 3:0] wid ,
output wire [31:0] wdata ,
output wire [ 3:0] wstrb ,
output wire wlast ,
output wire wvalid ,
input wire wready ,
(* mark_debug = "yes" *)output wire [31:0] wdata ,
(* mark_debug = "yes" *)output wire [ 3:0] wstrb ,
(* mark_debug = "yes" *)output wire wlast ,
(* mark_debug = "yes" *)output wire wvalid ,
(* mark_debug = "yes" *)input wire wready ,

input wire [ 3:0] bid ,
input wire [ 1:0] bresp ,
input wire bvalid ,
output wire bready ,

output wire [ 3:0] arid ,
output wire [31:0] araddr ,
output wire [ 7:0] arlen ,
output wire [ 2:0] arsize ,
(* mark_debug = "yes" *)output wire [31:0] araddr ,
(* mark_debug = "yes" *)output wire [ 3:0] arlen ,
(* mark_debug = "yes" *)output wire [ 2:0] arsize ,
output wire [ 1:0] arburst ,
output wire [ 1:0] arlock ,
output wire [ 3:0] arcache ,
output wire [ 2:0] arprot ,
output wire arvalid ,
input wire arready ,
(* mark_debug = "yes" *)output wire arvalid ,
(* mark_debug = "yes" *)input wire arready ,

input wire [ 3:0] rid ,
input wire [31:0] rdata ,
(* mark_debug = "yes" *)input wire [31:0] rdata ,
input wire [ 1:0] rresp ,
input wire rlast ,
input wire rvalid ,
output wire rready ,
(* mark_debug = "yes" *)input wire rlast ,
(* mark_debug = "yes" *)input wire rvalid ,
(* mark_debug = "yes" *)output wire rready ,
output wire [31:0] debug_wb_pc ,
output wire [3:0] debug_wb_rf_wen ,
output wire [4:0] debug_wb_rf_wnum ,
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1 change: 1 addition & 0 deletions source/sources_1/new/ifu/IF0_1_reg.sv
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Expand Up @@ -21,6 +21,7 @@ module IF0_1_reg(
logic headIsDS;
logic [31:0] dsAddr;
(* mark_debug = "yes" *)logic [31:0] PC;
(* mark_debug = "yes" *)wire debug_redirect = backend_if0.redirect;

assign if0_regs.PC = PC;
assign regs_nlp.PC = PC;
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53 changes: 49 additions & 4 deletions source/sources_1/new/interface/AXIInterface.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ module AXIInterface(
DCacheResp.axi dCacheResp
);

typedef enum { sRAddr, sRInst, sRData, sRDCache, sRRst } AXIRState;
typedef enum { sRAddr, sRInst, sRData, sRDCache, sRPendingResp,sRRst } AXIRState;
typedef enum { sWAddr, sWData, sWDCache, sWDResp, sWDCResp, sWRst } AXIWState;

AXIRState rState, nextRState, lastRState;
Expand Down Expand Up @@ -66,6 +66,37 @@ module AXIInterface(
logic lastDataBusy;
logic lastDCacheBusy;

logic instPendingReadResp;
logic dCPendingReadResp;
logic dataPendingReadResp;
logic [31:0] dataReadResp;

always_ff @(posedge clk) begin
if(rst) begin
dataReadResp <= 0;
instPendingReadResp <= `FALSE;
dCPendingReadResp <= `FALSE;
dataPendingReadResp <= `FALSE;
end else if(rState == sRData && axiReadData.valid && axiReadData.ready) begin
dataReadResp <= axiReadData.data;
instPendingReadResp <= `FALSE;
dCPendingReadResp <= `FALSE;
dataPendingReadResp <= `TRUE;
end else if(rState == sRDCache && axiReadData.valid && axiReadData.ready) begin
instPendingReadResp <= `FALSE;
dCPendingReadResp <= `TRUE;
dataPendingReadResp <= `FALSE;
end else if(rState == sRInst && axiReadData.valid && axiReadData.ready) begin
instPendingReadResp <= `TRUE;
dCPendingReadResp <= `FALSE;
dataPendingReadResp <= `FALSE;
end else if(rState == sRAddr) begin
instPendingReadResp <= `FALSE;
dCPendingReadResp <= `FALSE;
dataPendingReadResp <= `FALSE;
end
end

assign axiReadAddr.valid = rState == sRAddr && ((instReqBusy || (dataReqBusy && !dataReqWEn)) || (dCacheReqBusy && !dCacheReqWEn));
assign axiWriteAddr.valid = wState == sWAddr && ((dataReqBusy && dataReqWEn) || (dCacheReqBusy && dCacheReqWEn));

Expand Down Expand Up @@ -325,6 +356,7 @@ module AXIInterface(
axiReadAddr.length = 4'b0011; // burst 4
axiReadAddr.size = 3'b010;
axiReadAddr.burst = 2'b10;
axiReadAddr.protect = 3'b101;

dReadReady = `FALSE;
iReadReady = `FALSE;
Expand All @@ -341,18 +373,21 @@ module AXIInterface(
axiReadAddr.length = 4'b0011; // burst 4
axiReadAddr.size = 3'b010;
axiReadAddr.burst = 2'b10;
axiReadAddr.protect = 3'b001;
end else if(dataReqBusy && !dataReqWEn) begin
axiReadAddr.id = 4'h1;
axiReadAddr.address = dataReqAddr;
axiReadAddr.length = 4'b0000; // no burst
axiReadAddr.size = dataReqSize;
axiReadAddr.burst = 2'b00;
axiReadAddr.protect = 3'b001;
end else if(instReqBusy) begin
axiReadAddr.id = 4'h0;
axiReadAddr.address = instReqPC & 32'hFFFF_FFF0;
axiReadAddr.length = 4'b0011; // burst 4
axiReadAddr.size = 3'b010;
axiReadAddr.burst = 2'b10;
axiReadAddr.protect = 3'b101;
end

dReadReady = `FALSE;
Expand All @@ -366,24 +401,33 @@ module AXIInterface(
if(axiReadData.valid) begin
dReadReady = `TRUE;
dataResp.data = axiReadData.data;
end
end else if(dataPendingReadResp) begin
dReadReady = `TRUE;
dataResp.data = dataReadResp;
end
iReadReady = `FALSE;
dcReadReady = `FALSE;
end
sRInst: begin
axiReadData.ready = `TRUE;
if(axiReadData.last) begin
if(axiReadData.last && axiReadData.valid && axiReadData.ready) begin
iReadReady = `TRUE;
instResp.cacheLine = {axiReadData.data, iReadRes[95:0]};
end else if(instPendingReadResp) begin
iReadReady = `TRUE;
instResp.cacheLine = iReadRes;
end
dReadReady = `FALSE;
dcReadReady = `FALSE;
end
sRDCache: begin
axiReadData.ready = `TRUE;
if(axiReadData.last) begin
if(axiReadData.last && axiReadData.valid && axiReadData.ready) begin
dcReadReady = `TRUE;
dCacheResp.data = {axiReadData.data, dcReadRes[95:0]};
end else if(dCPendingReadResp) begin
dcReadReady = `TRUE;
dCacheResp.data = dcReadRes;
end
iReadReady = `FALSE;
dReadReady = `FALSE;
Expand All @@ -409,6 +453,7 @@ module AXIInterface(
axiWriteAddr.length = 4'b0011;
axiWriteAddr.size = 3'b010;
axiWriteAddr.burst = 2'b10;
axiWriteAddr.protect = 3'b001;
axiWriteData.id = 4'h0;
axiWriteData.strobe = 4'b1111;
axiWriteData.data = 0;
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11 changes: 5 additions & 6 deletions source/sources_1/new/interface/AXIWarp.sv
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Expand Up @@ -9,7 +9,7 @@ module AXIWarp(

output wire [ 3:0] awid ,
output wire [31:0] awaddr ,
output wire [ 7:0] awlen ,
output wire [ 3:0] awlen ,
output wire [ 2:0] awsize ,
output wire [ 1:0] awburst ,
output wire [ 1:0] awlock ,
Expand All @@ -32,7 +32,7 @@ module AXIWarp(

output wire [ 3:0] arid ,
output wire [31:0] araddr ,
output wire [ 7:0] arlen ,
output wire [ 3:0] arlen ,
output wire [ 2:0] arsize ,
output wire [ 1:0] arburst ,
output wire [ 1:0] arlock ,
Expand All @@ -51,12 +51,12 @@ module AXIWarp(

assign awid = axiWriteAddr.id;
assign awaddr = axiWriteAddr.address;
assign awlen[3:0] = axiWriteAddr.length;
assign awlen[7:4] = 4'h0;
assign awlen = axiWriteAddr.length;
assign awsize = axiWriteAddr.size;
assign awburst = axiWriteAddr.burst;
assign awlock = axiWriteAddr.lock;
assign awcache = axiWriteAddr.cache;
assign awsize = axiWriteAddr.size;
assign awprot = axiWriteAddr.protect;
assign awburst = axiWriteAddr.burst;
assign awvalid = axiWriteAddr.valid;

Expand All @@ -78,7 +78,6 @@ module AXIWarp(
assign arid = axiReadAddr.id;
assign araddr = axiReadAddr.address;
assign arlen[3:0] = axiReadAddr.length;
assign arlen[7:4] = 4'h0;
assign arsize = axiReadAddr.size;
assign arburst = axiReadAddr.burst;
assign arlock = axiReadAddr.lock;
Expand Down

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