Add mul, iCache bug fix

Superscalar-HIT-Core · Aug 4, 2020 · 71aad58 · 71aad58
1 parent 69d9939
commit 71aad58
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Showing 3 changed files with 22 additions and 1 deletion.
diff --git a/source/sources_1/new/decode.sv b/source/sources_1/new/decode.sv
@@ -250,6 +250,26 @@ module decode(
                     uOP1.dstwe      = `TRUE;
                     uOP1.valid      = `TRUE;
                 end
+                `MUL: begin
+                    uOP0.uOP        = MULTHI_U;
+                    uOP0.rs_type    = RS_MDU;
+                    uOP0.op0LAddr   = rs;
+                    uOP0.op1LAddr   = rt;
+                    uOP0.dstLAddr   = 0;    // discard high 32
+                    uOP0.op0re      = `TRUE;
+                    uOP0.op1re      = `TRUE;
+                    uOP0.dstwe      = `FALSE;
+
+                    uOP1.uOP        = MULTLO_U;
+                    uOP1.rs_type    = RS_MDU;
+                    uOP1.op0LAddr   = rs;
+                    uOP1.op1LAddr   = rt;
+                    uOP1.dstLAddr   = rd;
+                    uOP1.op0re      = `TRUE;
+                    uOP1.op1re      = `TRUE;
+                    uOP1.dstwe      = `TRUE;
+                    uOP1.valid      = `TRUE;
+                end
                 `AND: begin
                     uOP0.uOP        = AND_U;
                     uOP0.rs_type    = RS_ALU;

diff --git a/source/sources_1/new/defines/defines.svh b/source/sources_1/new/defines/defines.svh
@@ -108,6 +108,7 @@ typedef logic [5:0] ARFNum; // 逻辑寄存器编号(共34个)
 `define DIVU        32'b000000??_????????_00000000_00011011
 `define MULT        32'b000000??_????????_00000000_00011000
 `define MULTU       32'b000000??_????????_00000000_00011001
+`define MUL         32'b011100??_????????_?????000_00000010
 
 // logical
 `define AND         32'b000000??_????????_?????000_00100100

diff --git a/source/sources_1/new/ifu/ICache.sv b/source/sources_1/new/ifu/ICache.sv
@@ -310,7 +310,7 @@ module ICache(
                 if(rst) begin
                     nxtState = sReset;
                 end else if(flush) begin
-                    nxtState = sRunning;
+                    nxtState = sIdle;
                 end else if(!ctrl_iCache.pause) begin
                     nxtState = sRunning;
                 end else begin