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Merge branch 'master' of github.com:Superscalar-HIT-Core/SHIT-Core
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@Gyhanis
Gyhanis committed Aug 3, 2020
2 parents 101a2fc + f628eba commit a8d2874
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10 changes: 10 additions & 0 deletions source/sources_1/ip/tag_ram/tag_ram.xci
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Expand Up @@ -295,11 +295,21 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_A_Write_Rate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
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3 changes: 2 additions & 1 deletion source/sources_1/new/Commit.sv
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Expand Up @@ -35,9 +35,10 @@ module Commit(
logic isDS;
logic inst0Store;
logic inst1Store;
reg [5:0] ext_interrupt_signal;
(* mark_debug = "yes" *)reg [5:0] ext_interrupt_signal;
logic causeInt;
logic pendingInt;

always @(posedge clk) begin
if(rst) begin
ext_interrupt_signal <= 0;
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135 changes: 112 additions & 23 deletions source/sources_1/new/MyCPU.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,14 +7,22 @@ module mycpu_top(

input [5:0] ext_int,

<<<<<<< HEAD
(*mark_debug = "true"*)output wire [ 3:0] awid ,
(*mark_debug = "true"*)output wire [31:0] awaddr ,
output wire [ 7:0] awlen ,
output wire [ 2:0] awsize ,
=======
output wire [ 3:0] awid ,
(* mark_debug = "yes" *)output wire [31:0] awaddr ,
(* mark_debug = "yes" *)output wire [ 3:0] awlen ,
(* mark_debug = "yes" *)output wire [ 2:0] awsize ,
>>>>>>> bd15dcd3c36bdc0d3b4b681a506e36ae6ae2052a
output wire [ 1:0] awburst ,
output wire [ 1:0] awlock ,
output wire [ 3:0] awcache ,
output wire [ 2:0] awprot ,
<<<<<<< HEAD
(*mark_debug = "true"*)output wire awvalid ,
(*mark_debug = "true"*)input wire awready ,

Expand All @@ -24,29 +32,40 @@ module mycpu_top(
output wire wlast ,
(*mark_debug = "true"*)output wire wvalid ,
(*mark_debug = "true"*)input wire wready ,
=======
(* mark_debug = "yes" *)output wire awvalid ,
(* mark_debug = "yes" *)input wire awready ,

output wire [ 3:0] wid ,
(* mark_debug = "yes" *)output wire [31:0] wdata ,
(* mark_debug = "yes" *)output wire [ 3:0] wstrb ,
(* mark_debug = "yes" *)output wire wlast ,
(* mark_debug = "yes" *)output wire wvalid ,
(* mark_debug = "yes" *)input wire wready ,
>>>>>>> bd15dcd3c36bdc0d3b4b681a506e36ae6ae2052a

input wire [ 3:0] bid ,
input wire [ 1:0] bresp ,
input wire bvalid ,
output wire bready ,
(* mark_debug = "yes" *)input wire [ 1:0] bresp ,
(* mark_debug = "yes" *)input wire bvalid ,
(* mark_debug = "yes" *)output wire bready ,

output wire [ 3:0] arid ,
output wire [31:0] araddr ,
output wire [ 7:0] arlen ,
output wire [ 2:0] arsize ,
(* mark_debug = "yes" *)output wire [31:0] araddr ,
(* mark_debug = "yes" *)output wire [ 3:0] arlen ,
(* mark_debug = "yes" *)output wire [ 2:0] arsize ,
output wire [ 1:0] arburst ,
output wire [ 1:0] arlock ,
output wire [ 3:0] arcache ,
output wire [ 2:0] arprot ,
output wire arvalid ,
input wire arready ,
(* mark_debug = "yes" *)output wire arvalid ,
(* mark_debug = "yes" *)input wire arready ,

input wire [ 3:0] rid ,
input wire [31:0] rdata ,
(* mark_debug = "yes" *)input wire [31:0] rdata ,
input wire [ 1:0] rresp ,
input wire rlast ,
input wire rvalid ,
output wire rready ,
(* mark_debug = "yes" *)input wire rlast ,
(* mark_debug = "yes" *)input wire rvalid ,
(* mark_debug = "yes" *)output wire rready ,
output wire [31:0] debug_wb_pc ,
output wire [3:0] debug_wb_rf_wen ,
output wire [4:0] debug_wb_rf_wnum ,
Expand Down Expand Up @@ -273,6 +292,8 @@ module mycpu_top(
assign wake_reg_MDU_en = 0;
assign wake_reg_LSU = 0;
assign wake_reg_MDU = 0;
PRFNum alu0_wake_reg, alu1_wake_reg;
logic alu0_wake_ena, alu1_wake_ena;
// assign lsu_busy = 0;

wire dispatch_pause_req;
Expand Down Expand Up @@ -444,12 +465,12 @@ module mycpu_top(
.set_busy_num_0 (set_busy_num_0),
.set_busy_num_1 (set_busy_num_1),
// issued instructions(at most 4 instructions issue at a time)
.clr_busy_ALU0 (alu0WBReq.wen),
.clr_busy_ALU1 (alu1WBReq.wen),
.clr_busy_ALU0 (alu0_wake_ena),
.clr_busy_ALU1 (alu1_wake_ena),
.clr_busy_LSU (lsuWBReq.wen),
.clr_busy_MDU (mduWBReq.wen),
.clr_busy_num_ALU0 (alu0WBReq.rd),
.clr_busy_num_ALU1 (alu1WBReq.rd),
.clr_busy_num_ALU0 (alu0_wake_reg),
.clr_busy_num_ALU1 (alu1_wake_reg),
.clr_busy_num_LSU (lsuWBReq.rd),
.clr_busy_num_MDU (mduWBReq.rd),
.rd_num_l (scoreboard_rd_num_l_lsuiq2sb),
Expand Down Expand Up @@ -493,12 +514,12 @@ module mycpu_top(
.set_busy_num_0 (set_busy_num_0),
.set_busy_num_1 (set_busy_num_1),
// issued instructions(at most 4 instructions issue at a time)
.clr_busy_ALU0 (alu0WBReq.wen),
.clr_busy_ALU1 (alu1WBReq.wen),
.clr_busy_ALU0 (alu0_wake_ena),
.clr_busy_ALU1 (alu1_wake_ena),
.clr_busy_LSU (lsuWBReq.wen),
.clr_busy_MDU (mduWBReq.wen),
.clr_busy_num_ALU0 (alu0WBReq.rd),
.clr_busy_num_ALU1 (alu1WBReq.rd),
.clr_busy_num_ALU0 (alu0_wake_reg),
.clr_busy_num_ALU1 (alu1_wake_reg),
.clr_busy_num_LSU (lsuWBReq.rd),
.clr_busy_num_MDU (mduWBReq.rd),
.rd_num_l (scoreboard_rd_num_l_mduiq2sb),
Expand Down Expand Up @@ -531,23 +552,29 @@ module mycpu_top(
.issueBundle (issue_alu_inst_0),
.primPauseReq (`FALSE),
.rfBundle (alu0RFBundle),
.prfRequest (alu0RFReq)
.prfRequest (alu0RFReq),
.wakeReg (alu0_wake_reg),
.wakeEna (alu0_wake_ena)
);
Issue_RF_regs issue_alu1_regs(
.*,
.ctrl_issue_rf_regs (ctrl_issue_alu1_regs),
.issueBundle (issue_alu_inst_1),
.primPauseReq (`FALSE),
.rfBundle (alu1RFBundle),
.prfRequest (alu1RFReq)
.prfRequest (alu1RFReq),
.wakeReg (alu1_wake_reg),
.wakeEna (alu1_wake_ena)
);
Issue_RF_regs issue_lsu_regs(
.*,
.ctrl_issue_rf_regs (ctrl_issue_lsu_regs),
.issueBundle (issue_lsu_inst),
.primPauseReq (lsu_busy),
.rfBundle (lsuRFBundle),
.prfRequest (lsuRFReq)
.prfRequest (lsuRFReq),
.wakeReg(),
.wakeEna()
);
MDUIQ_RF_regs issue_mdu_regs(
.*,
Expand Down Expand Up @@ -743,5 +770,67 @@ module mycpu_top(
assign debug_regfile[k] = soc_axi_lite_top.cpu.prf_u.prfs_bank0[soc_axi_lite_top.cpu.rr.u_map_table.committed_rename_map_table_bank0[k]];
end
endgenerate

wire debug_pause_by_iCache = ctrl_iCache.pauseReq;
wire debug_pause_by_backend = ctrl_instBuffer.pauseReq;

wire debug_pause_by_alu = ~aluIQReady;
wire debug_pause_by_lsu = ~lsuIQReady;
wire debug_pause_by_mdu = ~mduIQReady;
wire debug_pause_by_rr = ~renameAllocatable;

wire debug_redirect = backend_if0.redirect;

logic [31:0] debug_frontend_pause_count;
logic [31:0] debug_backend_pause_count;

logic [31:0] debug_alu_pause_count;
logic [31:0] debug_lsu_pause_count;
logic [31:0] debug_mdu_pause_count;
logic [31:0] debug_rr_pause_count;

logic [31:0] debug_redirect_penalty;
logic [31:0] debug_total_cycle_count;

wire [31:0] debug_total_penalty = debug_frontend_pause_count + debug_backend_pause_count + debug_redirect_penalty;

wire debug_rob_dual_commit = rob_commit.valid && rob_commit.ready && commit.inst0Good && commit.inst1Good;
wire debug_rob_single_commit = rob_commit.valid && rob_commit.ready && !debug_rob_dual_commit;
wire debug_rob_no_commit = !debug_rob_dual_commit && !debug_rob_single_commit;

logic [31:0] debug_rob_dual_commit_count;
logic [31:0] debug_rob_single_commit_count;
logic [31:0] debug_rob_no_commit_count;

always_ff @ (posedge clk) begin
if(rst) begin
debug_frontend_pause_count <= 0;
debug_backend_pause_count <= 0;
debug_alu_pause_count <= 0;
debug_lsu_pause_count <= 0;
debug_mdu_pause_count <= 0;
debug_rr_pause_count <= 0;
debug_redirect_penalty <= 0;
debug_total_cycle_count <= 0;
debug_rob_dual_commit_count <= 0;
debug_rob_single_commit_count <= 0;
debug_rob_no_commit_count <= 0;
end else begin
if(debug_pause_by_iCache) debug_frontend_pause_count <= debug_frontend_pause_count + 1;
if(debug_pause_by_backend) debug_backend_pause_count <= debug_backend_pause_count + 1;
if(debug_pause_by_alu) debug_alu_pause_count <= debug_alu_pause_count + 1;
if(debug_pause_by_lsu) debug_lsu_pause_count <= debug_lsu_pause_count + 1;
if(debug_pause_by_mdu) debug_mdu_pause_count <= debug_mdu_pause_count + 1;
if(debug_pause_by_rr) debug_rr_pause_count <= debug_rr_pause_count + 1;
if(debug_redirect) debug_redirect_penalty <= debug_redirect_penalty + 12;
debug_total_cycle_count <= debug_total_cycle_count + 1;

if(debug_rob_dual_commit) debug_rob_dual_commit_count <= debug_rob_dual_commit_count + 1;
if(debug_rob_single_commit) debug_rob_single_commit_count <= debug_rob_single_commit_count + 1;
if(debug_rob_no_commit) debug_rob_no_commit_count <= debug_rob_no_commit_count + 1;
end
end

// synopsys translate_on

endmodule
7 changes: 5 additions & 2 deletions source/sources_1/new/exu/Issue_RF_regs.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,9 @@ module Issue_RF_regs(
input UOPBundle issueBundle,
input wire primPauseReq,
output UOPBundle rfBundle,
output PRFrNums prfRequest
output PRFrNums prfRequest,
output PRFNum wakeReg,
output wakeEna
);

always_ff @ (posedge clk) begin
Expand All @@ -27,5 +29,6 @@ module Issue_RF_regs(
prfRequest.rs1 <= issueBundle.op1PAddr;
end
end

assign wakeReg = rfBundle.dstPAddr;
assign wakeEna = rfBundle.dstwe && rfBundle.valid;
endmodule
94 changes: 48 additions & 46 deletions source/sources_1/new/ifu/ICache.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -487,52 +487,54 @@ module ICache(
iCache_regs.inst0.valid = `FALSE;
iCache_regs.inst1.valid = `FALSE;
`ifdef USE_RECOVER_WRITE_ICACHE
casex (age[lineAddress])
3'b?11: begin // replace hit0
tag0IO.writeEn = `TRUE;
tag0IO.address = recoverPCReg[9:4];
tag0IO.dataIn = recoverTag;
data0IO.writeEn = `TRUE;
data0IO.address = recoverPCReg[9:4];
data0IO.dataIn = instResp.cacheLine;
nxtAge[lineAddress][0] = 1'b0;
nxtAge[lineAddress][1] = 1'b0;
nxtValid[0][lineAddress] = `TRUE;
end
3'b?01: begin // replace hit1
tag1IO.writeEn = `TRUE;
tag1IO.address = recoverPCReg[9:4];
tag1IO.dataIn = recoverTag;
data1IO.writeEn = `TRUE;
data1IO.address = recoverPCReg[9:4];
data1IO.dataIn = instResp.cacheLine;
nxtAge[lineAddress][0] = 1'b0;
nxtAge[lineAddress][1] = 1'b1;
nxtValid[1][lineAddress] = `TRUE;
end
3'b1?0: begin // replace hit2
tag2IO.writeEn = `TRUE;
tag2IO.address = recoverPCReg[9:4];
tag2IO.dataIn = recoverTag;
data2IO.writeEn = `TRUE;
data2IO.address = recoverPCReg[9:4];
data2IO.dataIn = instResp.cacheLine;
nxtAge[lineAddress][0] = 1'b1;
nxtAge[lineAddress][2] = 1'b0;
nxtValid[2][lineAddress] = `TRUE;
end
3'b0?0: begin // replace hit3
tag3IO.writeEn = `TRUE;
tag3IO.address = recoverPCReg[9:4];
tag3IO.dataIn = recoverTag;
data3IO.writeEn = `TRUE;
data3IO.address = recoverPCReg[9:4];
data3IO.dataIn = instResp.cacheLine;
nxtAge[lineAddress][0] = 1'b1;
nxtAge[lineAddress][2] = 1'b1;
nxtValid[3][lineAddress] = `TRUE;
end
endcase
if(!hit) begin
casex (age[recoverPCReg[9:4]])
3'b?11: begin // replace hit0
tag0IO.writeEn = `TRUE;
tag0IO.address = recoverPCReg[9:4];
tag0IO.dataIn = recoverTag;
data0IO.writeEn = `TRUE;
data0IO.address = recoverPCReg[9:4];
data0IO.dataIn = instResp.cacheLine;
nxtAge[recoverPCReg[9:4]][0] = 1'b0;
nxtAge[recoverPCReg[9:4]][1] = 1'b0;
nxtValid[0][recoverPCReg[9:4]] = `TRUE;
end
3'b?01: begin // replace hit1
tag1IO.writeEn = `TRUE;
tag1IO.address = recoverPCReg[9:4];
tag1IO.dataIn = recoverTag;
data1IO.writeEn = `TRUE;
data1IO.address = recoverPCReg[9:4];
data1IO.dataIn = instResp.cacheLine;
nxtAge[recoverPCReg[9:4]][0] = 1'b0;
nxtAge[recoverPCReg[9:4]][1] = 1'b1;
nxtValid[1][recoverPCReg[9:4]] = `TRUE;
end
3'b1?0: begin // replace hit2
tag2IO.writeEn = `TRUE;
tag2IO.address = recoverPCReg[9:4];
tag2IO.dataIn = recoverTag;
data2IO.writeEn = `TRUE;
data2IO.address = recoverPCReg[9:4];
data2IO.dataIn = instResp.cacheLine;
nxtAge[recoverPCReg[9:4]][0] = 1'b1;
nxtAge[recoverPCReg[9:4]][2] = 1'b0;
nxtValid[2][recoverPCReg[9:4]] = `TRUE;
end
3'b0?0: begin // replace hit3
tag3IO.writeEn = `TRUE;
tag3IO.address = recoverPCReg[9:4];
tag3IO.dataIn = recoverTag;
data3IO.writeEn = `TRUE;
data3IO.address = recoverPCReg[9:4];
data3IO.dataIn = instResp.cacheLine;
nxtAge[recoverPCReg[9:4]][0] = 1'b1;
nxtAge[recoverPCReg[9:4]][2] = 1'b1;
nxtValid[3][recoverPCReg[9:4]] = `TRUE;
end
endcase
end
`endif
end else begin
ctrl_iCache.pauseReq = `TRUE;
Expand Down
3 changes: 2 additions & 1 deletion source/sources_1/new/ifu/IF0_1_reg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,8 @@ module IF0_1_reg(

logic headIsDS;
logic [31:0] dsAddr;
logic [31:0] PC;
(* mark_debug = "yes" *)logic [31:0] PC;
(* mark_debug = "yes" *)wire debug_redirect = backend_if0.redirect;

assign if0_regs.PC = PC;
assign regs_nlp.PC = PC;
Expand Down
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