fix writeback

Superscalar-HIT-Core · Aug 2, 2020 · ab2d078 · ab2d078
1 parent 7af133b
commit ab2d078
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Showing 4 changed files with 9 additions and 19 deletions.
diff --git a/source/sources_1/ip/tag_ram/tag_ram.xci b/source/sources_1/ip/tag_ram/tag_ram.xci
@@ -295,21 +295,11 @@
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_A_Write_Rate" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>

diff --git a/source/sources_1/new/LSU/dcache.sv b/source/sources_1/new/LSU/dcache.sv
@@ -90,8 +90,8 @@ module dcache(
             wp2dc.dout = dbr1.data;
         else
             case(lru[index_reg2])
-            1'b0: wp2dc.dout = dbr0.data;
-            1'b1: wp2dc.dout = dbr1.data;
+            1'b0: wp2dc.dout = dbr1.data;
+            1'b1: wp2dc.dout = dbr0.data;
             endcase
 
     always_ff @(posedge g.clk)

diff --git a/source/sources_1/new/LSU/writeback_handler.sv b/source/sources_1/new/LSU/writeback_handler.sv
@@ -12,7 +12,7 @@ module writeback_handler(
     always_ff @(posedge g.clk)
         if(!g.resetn)
             valid <= 1'b0;
-        else if(mh2wbh.valid & dc2mem.mready)
+        else if(mh2wbh.valid & ~dc2mem.mready)
             valid <= 1'b1;
         else if(dc2mem.mready)
             valid <= 1'b0;

diff --git a/source/sources_1/new/ifu/NLP.sv b/source/sources_1/new/ifu/NLP.sv
@@ -76,11 +76,11 @@ module NLP(
             if (if3_nlp.update.valid && if3UpdateMatch) begin
                 for(integer i = 0; i < 16; i++) begin
                     if(data[i].valid && data[i].pc == if3_nlp.update.pc) begin
-                        data[i].targetAddr     = if3_nlp.update.target;
+                        data[i].targetAddr     <= if3_nlp.update.target;
                         if(if3_nlp.update.shouldTake) begin
-                            data[i].bimState   = if3_nlp.update.bimState == 2'b11 ? 2'b11 : if3_nlp.update.bimState + 1;
+                            data[i].bimState   <= if3_nlp.update.bimState == 2'b11 ? 2'b11 : if3_nlp.update.bimState + 1;
                         end else begin
-                            data[i].bimState   = if3_nlp.update.bimState == 2'b00 ? 2'b00 : if3_nlp.update.bimState - 1;
+                            data[i].bimState   <= if3_nlp.update.bimState == 2'b00 ? 2'b00 : if3_nlp.update.bimState - 1;
                         end
                         break;
                     end
@@ -95,11 +95,11 @@ module NLP(
             if (backend_nlp.update.valid && backendUpdateMatch) begin
                 for(integer i = 0; i < 16; i++) begin
                     if(data[i].valid && data[i].pc == backend_nlp.update.pc) begin
-                        data[i].targetAddr     = backend_nlp.update.target;
+                        data[i].targetAddr     <= backend_nlp.update.target;
                         if(backend_nlp.update.shouldTake) begin
-                            data[i].bimState   = backend_nlp.update.bimState == 2'b11 ? 2'b11 : backend_nlp.update.bimState + 1;
+                            data[i].bimState   <= backend_nlp.update.bimState == 2'b11 ? 2'b11 : backend_nlp.update.bimState + 1;
                         end else begin
-                            data[i].bimState   = backend_nlp.update.bimState == 2'b00 ? 2'b00 : backend_nlp.update.bimState - 1;
+                            data[i].bimState   <= backend_nlp.update.bimState == 2'b00 ? 2'b00 : backend_nlp.update.bimState - 1;
                         end
                         break;
                     end