runs @80MHz score = 44.3

source/sources_1/new/CP0.sv

@@ -25,9 +25,9 @@ module CP0(
     logic [31:0]    Count;
     logic [31:0]    EntryHi;
     logic [31:0]    Compare;
-    (* mark_debug = "yes" *)logic [31:0]    Status;
-    (* mark_debug = "yes" *)logic [31:0]    Cause;
-    (* mark_debug = "yes" *)logic [31:0]    EPc;
+    logic [31:0]    Status;
+    logic [31:0]    Cause;
+    logic [31:0]    EPc;
     logic [31:0]    PRId;
     logic [31:0]    EBase;
     logic [31:0]    Config;

source/sources_1/new/Commit.sv

@@ -35,13 +35,13 @@ module Commit(
     logic           isDS;
     logic           inst0Store;
     logic           inst1Store;
-    (* mark_debug = "yes" *) reg [5:0] ext_interrupt_signal;
-    (* mark_debug = "yes" *) logic causeInt;
-    (* mark_debug = "yes" *) logic           pendingInt;
-    (* mark_debug = "yes" *) wire [31:0] debug_rob_pc0 = rob_commit.uOP0.pc;
-    (* mark_debug = "yes" *) wire [31:0] debug_rob_pc1 = rob_commit.uOP1.pc;
-    (* mark_debug = "yes" *) wire busy_pc0 = rob_commit.uOP0.busy;
-    (* mark_debug = "yes" *) wire busy_pc1 = rob_commit.uOP1.busy;
+    reg [5:0] ext_interrupt_signal;
+    logic causeInt;
+    logic           pendingInt;
+    wire [31:0] debug_rob_pc0 = rob_commit.uOP0.pc;
+    wire [31:0] debug_rob_pc1 = rob_commit.uOP1.pc;
+    wire busy_pc0 = rob_commit.uOP0.busy;
+    wire busy_pc1 = rob_commit.uOP1.busy;
     always @(posedge clk)   begin
         if(rst) begin
             ext_interrupt_signal <= 0;

source/sources_1/new/LSU/LSU.sv

@@ -12,16 +12,16 @@ module LSU(
     input   UOPBundle       uOP,
     input   PRFrData        oprands,
     output  PRFwInfo        wbData,
-    (* mark_debug = "yes" *)    output                  half_full,
+    output                  half_full,
     FU_ROB.fu               lsu_commit_reg,
     DataReq.lsu             dataReq,
     DataResp.lsu            dataResp,
     DCacheReq.dCache        dCacheReq,
     DCacheResp.dCache       dCacheResp,
     UncachedLoadInfo.lsu    uncachedLoadInfo
     );
-    (* mark_debug = "yes" *) wire [31:0] LSU_execute_PC = uOP.pc;
-    (* mark_debug = "yes" *) wire LSU_execute_valid = uOP.valid;
+    wire [31:0] LSU_execute_PC = uOP.pc;
+    wire LSU_execute_valid = uOP.valid;
     assign pauseReq = 1'b0;
     assign flushReq = 1'b0;
     logic r_busy;
@@ -147,8 +147,8 @@ module LSU(
     assign lsu2rt.rfin = lsu2prf.valid;
     assign lsu2rt.rid = lsu2prf.id;
 
-(* mark_debug = "yes" *)    assign lsu_commit_reg.setFinish = lsu2rob.valid;
-(* mark_debug = "yes" *)    assign lsu_commit_reg.id = lsu2rob.id;
+    assign lsu_commit_reg.setFinish = lsu2rob.valid;
+    assign lsu_commit_reg.id = lsu2rob.id;
     assign lsu_commit_reg.setException = lsu2rob.set_ex;
     assign lsu_commit_reg.exceptionType = (lsu2rob.ls == 1'b1) ? ExcAddressErrS : ExcAddressErrL;
     assign lsu_commit_reg.BadVAddr = lsu2rob.bad_addr;

source/sources_1/new/MyCPU.sv

@@ -8,45 +8,45 @@ module mycpu_top(
     input [5:0] ext_int,
 
     output wire [ 3:0]  awid      ,
-    (* mark_debug = "yes" *)output wire [31:0]  awaddr    ,
-    (* mark_debug = "yes" *)output wire [ 3:0]  awlen     ,
-    (* mark_debug = "yes" *)output wire [ 2:0]  awsize    ,
+    output wire [31:0]  awaddr    ,
+    output wire [ 3:0]  awlen     ,
+    output wire [ 2:0]  awsize    ,
     output wire [ 1:0]  awburst   ,
     output wire [ 1:0]  awlock    ,
     output wire [ 3:0]  awcache   ,
     output wire [ 2:0]  awprot    ,
-    (* mark_debug = "yes" *)output wire         awvalid   ,
-    (* mark_debug = "yes" *)input  wire         awready   ,
+    output wire         awvalid   ,
+    input  wire         awready   ,
 
     output wire [ 3:0]  wid       ,
-    (* mark_debug = "yes" *)output wire [31:0]  wdata     ,
-    (* mark_debug = "yes" *)output wire [ 3:0]  wstrb     ,
-    (* mark_debug = "yes" *)output wire         wlast     ,
-    (* mark_debug = "yes" *)output wire         wvalid    ,
-    (* mark_debug = "yes" *)input  wire         wready    ,
+    output wire [31:0]  wdata     ,
+    output wire [ 3:0]  wstrb     ,
+    output wire         wlast     ,
+    output wire         wvalid    ,
+    input  wire         wready    ,
 
     input  wire [ 3:0]  bid       ,
-    (* mark_debug = "yes" *)input  wire [ 1:0]  bresp     ,
-    (* mark_debug = "yes" *)input  wire         bvalid    ,
-    (* mark_debug = "yes" *)output wire         bready    ,
+    input  wire [ 1:0]  bresp     ,
+    input  wire         bvalid    ,
+    output wire         bready    ,
 
     output wire [ 3:0]  arid      ,
-    (* mark_debug = "yes" *)output wire [31:0]  araddr    ,
-    (* mark_debug = "yes" *)output wire [ 3:0]  arlen     ,
-    (* mark_debug = "yes" *)output wire [ 2:0]  arsize    ,
+    output wire [31:0]  araddr    ,
+    output wire [ 3:0]  arlen     ,
+    output wire [ 2:0]  arsize    ,
     output wire [ 1:0]  arburst   ,
     output wire [ 1:0]  arlock    ,
     output wire [ 3:0]  arcache   ,
     output wire [ 2:0]  arprot    ,
-    (* mark_debug = "yes" *)output wire         arvalid   ,
-    (* mark_debug = "yes" *)input  wire         arready   ,
+    output wire         arvalid   ,
+    input  wire         arready   ,
 
     input  wire [ 3:0]  rid       ,
-    (* mark_debug = "yes" *)input  wire [31:0]  rdata     ,
+    input  wire [31:0]  rdata     ,
     input  wire [ 1:0]  rresp     ,
-    (* mark_debug = "yes" *)input  wire         rlast     ,
-    (* mark_debug = "yes" *)input  wire         rvalid    ,
-    (* mark_debug = "yes" *)output wire         rready    ,
+    input  wire         rlast     ,
+    input  wire         rvalid    ,
+    output wire         rready    ,
     output wire [31:0]  debug_wb_pc            ,
     output wire [3:0]   debug_wb_rf_wen        ,
     output wire [4:0]   debug_wb_rf_wnum       ,

source/sources_1/new/defines/defines.svh

@@ -15,9 +15,9 @@
 `define CMPQ_SEL_UP2    2'b11
 
 `define UOP_WIDTH   7:0
-`define ROB_SIZE    64
+`define ROB_SIZE    32
 `define ROB_ID_W    1+`ROB_ADDR_W
-`define ROB_ADDR_W  5:0
+`define ROB_ADDR_W  4:0
 `define TRUE        1'b1
 `define FALSE       1'b0
 

source/sources_1/new/dispatch.sv

@@ -16,35 +16,31 @@ module dispatch(
     output ALU_Queue_Meta rs_alu_dout_0, rs_alu_dout_1,
     output MDU_Queue_Meta rs_mdu_dout_0,
     output LSU_Queue_Meta rs_lsu_dout_0, rs_lsu_dout_1,
-    // Dispatch阶段设置busy位，写Scoreboard
     output PRFNum dispatch_inst0_wnum,
     output PRFNum dispatch_inst1_wnum,
     output dispatch_inst0_wen,
     output dispatch_inst1_wen,
     Dispatch_ROB.dispatch dispatch_rob,
     output pause_req
     );
-// 分配判断
-(* mark_debug = "yes" *) wire [31:0] dispatch_input_pc0 = inst_0_ops.pc;
-(* mark_debug = "yes" *) wire [31:0] dispatch_input_pc1 = inst_1_ops.pc;
+wire [31:0] dispatch_input_pc0 = inst_0_ops.pc;
+wire [31:0] dispatch_input_pc1 = inst_1_ops.pc;
 wire robEmpty = dispatch_rob.empty;
 wire hasPrivInst =  (inst_0_ops.valid && inst_0_ops.isPriv) || 
                     (inst_1_ops.valid && inst_1_ops.isPriv);
 wire slotsFull = inst_0_ops.valid && inst_1_ops.valid;
 wire PrivInstisDS = (inst_1_ops.valid && inst_1_ops.isPriv && inst_1_ops.isDS);
-wire passThrough = ~hasPrivInst || PrivInstisDS;                // 不需要暂停，直接传�过�
+wire passThrough = ~hasPrivInst || PrivInstisDS;                
 reg pause_req_cp0;
-assign pause_req = pause_req_cp0;           // rob的已经在外面处理�
-// 对ROB发来的ROB ID进行处理
-wire [7:0] robID_0, robID_1;
-(* mark_debug = "yes" *) assign robID_0 = { dispatch_rob.robID[6:0], 1'b0 } ;
-(* mark_debug = "yes" *) assign robID_1 = { dispatch_rob.robID[6:0], 1'b1 } ;
+assign pause_req = pause_req_cp0;           
+wire [`ROB_ID_W] robID_0, robID_1;
+assign robID_0 = { dispatch_rob.robID[`ROB_ADDR_W], 1'b0 } ;
+assign robID_1 = { dispatch_rob.robID[`ROB_ADDR_W], 1'b1 } ;
 
-// 根据当前的状态，对当前的两个ops进行reorder (TODO) //////////////////////////////
 UOPBundle inst_0_ops_reordered, inst_1_ops_reordered;
 // Handle CP0 Logic
 typedef enum bit[2:0] { IDLE, WAIT_ROB_SLOT0, WR_ROB_SLOT0, WAIT_ROB_SLOT1, WR_ROB_SLOT1, DONE } dispatchState;
-(* mark_debug = "yes" *)dispatchState current_state, next_state;
+dispatchState current_state, next_state;
 
 always @(posedge clk)   begin
     if(rst) begin
@@ -54,9 +50,6 @@ always @(posedge clk)   begin
     end
 end
 
-// CP0?????????ROB????????????LSU?Store Buffer??????
-// ??????????????????????CP0????????ROB???????????????
-// ?LSU???????????????CP0??????????CP0????????Set Unbusy?????Set busy
 always_comb begin
     next_state = IDLE;
     case(current_state)
@@ -86,7 +79,7 @@ always_comb begin
     endcase
 end
 
-always_comb begin   // 在此处完成reorder
+always_comb begin  
     pause_req_cp0 = 0;
     inst_0_ops_reordered = 0;
     inst_1_ops_reordered = 0;
@@ -138,8 +131,8 @@ always_comb begin   // 在此处完成reorder
     inst_1_ops_reordered.id = robID_1;
     inst_1_ops_reordered.busy = ( inst_1_ops_reordered.valid && inst_1_ops_reordered.uOP != NOP_U && inst_1_ops_reordered.uOP != MDBUBBLE_U );
 end
-(* mark_debug = "yes" *) wire [31:0] dispatch_out_pc0 = inst_0_ops_reordered.pc;
-(* mark_debug = "yes" *) wire [31:0] dispatch_out_pc1 = inst_1_ops_reordered.pc;
+wire [31:0] dispatch_out_pc0 = inst_0_ops_reordered.pc;
+wire [31:0] dispatch_out_pc1 = inst_1_ops_reordered.pc;
 wire inst0_isMul, inst1_isMul;
 wire inst0_isStore, inst1_isStore;
 assign inst0_isMul =    (inst_0_ops_reordered.uOP == MULTHI_U ) || 
@@ -167,7 +160,7 @@ wire inst_1_is_alu = (inst_1_ops_reordered.rs_type == RS_ALU) && inst_1_ops_reor
 wire inst_0_is_mdu = (inst_0_ops_reordered.rs_type == RS_MDU) && inst_0_ops_reordered.valid;
 wire inst_0_is_lsu = (inst_0_ops_reordered.rs_type == RS_LSU) && inst_0_ops_reordered.valid;
 wire inst_1_is_lsu = (inst_1_ops_reordered.rs_type == RS_LSU) && inst_1_ops_reordered.valid;
-// 每个指令的操作数是否已经准备好（这里只是设置是否读寄存器�
+// 
 wire inst0_r0_ren = inst_0_ops_reordered.op0re && (|inst_0_ops_reordered.op0LAddr);
 wire inst0_r1_ren = inst_0_ops_reordered.op1re && (|inst_0_ops_reordered.op1LAddr);
 wire inst1_r0_ren = inst_1_ops_reordered.op0re && (|inst_1_ops_reordered.op0LAddr);
@@ -178,8 +171,7 @@ assign inst0_rdy.prs2_rdy = ~(inst0_r1_ren);
 assign inst1_rdy.prs1_rdy = ~(inst1_r0_ren);
 assign inst1_rdy.prs2_rdy = ~(inst1_r1_ren);
 
-// 分发出去的指令是否会写寄存器
-// 用于分发阶段的setBusy(各个Scoreboard)
+
 assign dispatch_inst0_wnum = inst_0_ops_reordered.dstPAddr;
 assign dispatch_inst1_wnum = inst_1_ops_reordered.dstPAddr;
 assign dispatch_inst0_wen = inst_0_ops_reordered.dstwe && inst_0_ops_reordered.valid;

source/sources_1/new/exu/ALU.sv

@@ -12,8 +12,8 @@ module ALU(
     );
 wire overflow;
 logic j2BadVaddr;
-(* mark_debug = "yes" *) wire [31:0] ALUPC = uops.pc;
-(* mark_debug = "yes" *) wire ALU_Valid = uops.valid;
+wire [31:0] ALUPC = uops.pc;
+wire ALU_Valid = uops.valid;
 // trigger on taken bad jump addr. If error is a ExcAddressErrIF, SET BOTH EPC AND BADVADDR TO BADVADDR
 assign j2BadVaddr = alu_rob.setBranchStatus &&  alu_rob.branchTaken && (|alu_rob.branchAddr[1:0]);
 assign alu_rob.setFinish = uops.valid;

source/sources_1/new/ifu/IF0_1_reg.sv

@@ -20,8 +20,8 @@ module IF0_1_reg(
 
     logic           headIsDS;
     logic [31:0]    dsAddr;
-    (* mark_debug = "yes" *)logic [31:0]    PC;
-    (* mark_debug = "yes" *)wire debug_redirect = backend_if0.redirect;
+    logic [31:0]    PC;
+    wire debug_redirect = backend_if0.redirect;
 
     assign if0_regs.PC      = PC;
     assign regs_nlp.PC      = PC;

source/sources_1/new/ifu/IF_3.sv

@@ -234,22 +234,27 @@ module IF_3(
     end
 
     // nlp update info
-    always_comb begin
-        if3_nlp.update = 0;
-        if(if3_regs.inst0.valid && (pred_valid && inst0IsCtrl || (if3_regs.inst0.isJ && (!inst0Jr || (inst0Jr && if3_regs.inst0.nlpInfo.valid))))) begin
-            if3_nlp.update.pc          = if3_regs.inst0.pc;
-            if3_nlp.update.target      = if3_regs.inst0.predAddr;
-            if3_nlp.update.bimState    = if3_regs.inst0.nlpInfo.valid ? if3_regs.inst0.nlpInfo.bimState : 2'b01;
-            if3_nlp.update.shouldTake  = if3_regs.inst0.predTaken;
-            if3_nlp.update.valid       = `TRUE;
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            if3_nlp.update.pc          <= 0;
+            if3_nlp.update.target      <= 0;
+            if3_nlp.update.bimState    <= 0;
+            if3_nlp.update.shouldTake  <= 0;
+            if3_nlp.update.valid       <= 0;
+        end else if(if3_regs.inst0.valid && (pred_valid && inst0IsCtrl || (if3_regs.inst0.isJ && (!inst0Jr || (inst0Jr && if3_regs.inst0.nlpInfo.valid))))) begin
+            if3_nlp.update.pc          <= if3_regs.inst0.pc;
+            if3_nlp.update.target      <= if3_regs.inst0.predAddr;
+            if3_nlp.update.bimState    <= if3_regs.inst0.nlpInfo.valid ? if3_regs.inst0.nlpInfo.bimState : 2'b01;
+            if3_nlp.update.shouldTake  <= if3_regs.inst0.predTaken;
+            if3_nlp.update.valid       <= `TRUE;
         end else if(if3_regs.inst1.valid && (pred_valid && inst1IsCtrl || (if3_regs.inst1.isJ && (!inst1Jr || (inst1Jr && if3_regs.inst1.nlpInfo.valid))))) begin
-            if3_nlp.update.pc          = if3_regs.inst1.pc;
-            if3_nlp.update.target      = if3_regs.inst1.predAddr;
-            if3_nlp.update.bimState    = if3_regs.inst1.nlpInfo.valid ? if3_regs.inst1.nlpInfo.bimState : 2'b01;
-            if3_nlp.update.shouldTake  = if3_regs.inst1.predTaken;
-            if3_nlp.update.valid       = `TRUE;
+            if3_nlp.update.pc          <= if3_regs.inst1.pc;
+            if3_nlp.update.target      <= if3_regs.inst1.predAddr;
+            if3_nlp.update.bimState    <= if3_regs.inst1.nlpInfo.valid ? if3_regs.inst1.nlpInfo.bimState : 2'b01;
+            if3_nlp.update.shouldTake  <= if3_regs.inst1.predTaken;
+            if3_nlp.update.valid       <= `TRUE;
         end else begin
-            if3_nlp.update.valid       = `FALSE;
+            if3_nlp.update.valid       <= `FALSE;
         end
     end
 endmodule