IC implementation of Systolic Array for TPU

Simulations and designs for bit serial ALU implemented in TTL circuitry. Also bit serial cpu architectures - all simulated using H. Neeman's "Digital" simulator

Basic floating-point components for RISC-V processors

Fully opensource spiking neural network accelerator

A graphical processor simulator and assembly editor for the RISC-V ISA

Interface Protocol in Verilog

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.