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cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
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Prepares for changing cpu_single_step() argument to CPUState.

Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
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@afaerber
afaerber committed Jul 23, 2013
1 parent 801c4c2 commit ed2803d
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Showing 23 changed files with 78 additions and 52 deletions.
2 changes: 1 addition & 1 deletion cpu-exec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -297,7 +297,7 @@ int cpu_exec(CPUArchState *env)
for(;;) {
interrupt_request = cpu->interrupt_request;
if (unlikely(interrupt_request)) {
if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
/* Mask out external interrupts for this step. */
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}
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2 changes: 1 addition & 1 deletion cpus.c
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Expand Up @@ -1186,7 +1186,7 @@ static void tcg_exec_all(void)
CPUArchState *env = cpu->env_ptr;

qemu_clock_enable(vm_clock,
(env->singlestep_enabled & SSTEP_NOTIMER) == 0);
(cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);

if (cpu_can_run(cpu)) {
r = tcg_cpu_exec(env);
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10 changes: 6 additions & 4 deletions exec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -588,11 +588,13 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
void cpu_single_step(CPUArchState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
if (env->singlestep_enabled != enabled) {
env->singlestep_enabled = enabled;
if (kvm_enabled())
CPUState *cpu = ENV_GET_CPU(env);

if (cpu->singlestep_enabled != enabled) {
cpu->singlestep_enabled = enabled;
if (kvm_enabled()) {
kvm_update_guest_debug(env, 0);
else {
} else {
/* must flush all the translated code to avoid inconsistencies */
/* XXX: only flush what is necessary */
tb_flush(env);
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1 change: 0 additions & 1 deletion include/exec/cpu-defs.h
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Expand Up @@ -170,7 +170,6 @@ typedef struct CPUWatchpoint {
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
int singlestep_enabled; \
\
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
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2 changes: 2 additions & 0 deletions include/qom/cpu.h
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Expand Up @@ -133,6 +133,7 @@ struct kvm_run;
* @stopped: Indicates the CPU has been artificially stopped.
* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
* CPU and return to its top level loop.
* @singlestep_enabled: Flags for single-stepping.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
* @next_cpu: Next CPU sharing TB cache.
Expand Down Expand Up @@ -165,6 +166,7 @@ struct CPUState {
volatile sig_atomic_t exit_request;
volatile sig_atomic_t tcg_exit_req;
uint32_t interrupt_request;
int singlestep_enabled;

void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
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2 changes: 1 addition & 1 deletion kvm-all.c
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Expand Up @@ -1890,7 +1890,7 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)

data.dbg.control = reinject_trap;

if (env->singlestep_enabled) {
if (cpu->singlestep_enabled) {
data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
}
kvm_arch_update_guest_debug(cpu, &data.dbg);
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3 changes: 2 additions & 1 deletion target-alpha/translate.c
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Expand Up @@ -3388,6 +3388,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUAlphaState *env = &cpu->env;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
Expand All @@ -3406,7 +3407,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
ctx.pc = pc_start;
ctx.mem_idx = cpu_mmu_index(env);
ctx.implver = env->implver;
ctx.singlestep_enabled = env->singlestep_enabled;
ctx.singlestep_enabled = cs->singlestep_enabled;

/* ??? Every TB begins with unset rounding mode, to be initialized on
the first fp insn of the TB. Alternately we could define a proper
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7 changes: 4 additions & 3 deletions target-arm/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9911,6 +9911,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
CPUBreakpoint *bp;
Expand All @@ -9930,7 +9931,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,

dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->singlestep_enabled = env->singlestep_enabled;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->condjmp = 0;
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
Expand Down Expand Up @@ -10080,7 +10081,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* ensures prefetch aborts occur at the right place. */
num_insns ++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
!env->singlestep_enabled &&
!cs->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
Expand All @@ -10097,7 +10098,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
if (unlikely(env->singlestep_enabled)) {
if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
gen_set_condexec(dc);
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7 changes: 4 additions & 3 deletions target-cris/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3165,6 +3165,7 @@ static inline void
gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUCRISState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
Expand Down Expand Up @@ -3197,7 +3198,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
dc->is_jmp = DISAS_NEXT;
dc->ppc = pc_start;
dc->pc = pc_start;
dc->singlestep_enabled = env->singlestep_enabled;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->flags_uptodate = 1;
dc->flagx_known = 1;
dc->flags_x = tb->flags & X_FLAG;
Expand Down Expand Up @@ -3337,7 +3338,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,

/* If we are rexecuting a branch due to exceptions on
delay slots dont break. */
if (!(tb->pc & 1) && env->singlestep_enabled) {
if (!(tb->pc & 1) && cs->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
Expand Down Expand Up @@ -3370,7 +3371,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,

cris_evaluate_flags(dc);

if (unlikely(env->singlestep_enabled)) {
if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(env_pc, npc);
}
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6 changes: 4 additions & 2 deletions target-i386/kvm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1594,6 +1594,7 @@ static int kvm_get_vcpu_events(X86CPU *cpu)

static int kvm_guest_debug_workarounds(X86CPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int ret = 0;
unsigned long reinject_trap = 0;
Expand All @@ -1616,7 +1617,7 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu)
* reinject them via SET_GUEST_DEBUG.
*/
if (reinject_trap ||
(!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
(!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
ret = kvm_update_guest_debug(env, reinject_trap);
}
return ret;
Expand Down Expand Up @@ -2042,13 +2043,14 @@ static CPUWatchpoint hw_watchpoint;
static int kvm_handle_debug(X86CPU *cpu,
struct kvm_debug_exit_arch *arch_info)
{
CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int ret = 0;
int n;

if (arch_info->exception == 1) {
if (arch_info->dr6 & (1 << 14)) {
if (env->singlestep_enabled) {
if (cs->singlestep_enabled) {
ret = EXCP_DEBUG;
}
} else {
Expand Down
5 changes: 3 additions & 2 deletions target-i386/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8255,6 +8255,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
Expand All @@ -8281,7 +8282,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
dc->singlestep_enabled = env->singlestep_enabled;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->cs_base = cs_base;
Expand All @@ -8302,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
|| (flags & HF_SOFTMMU_MASK)
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7 changes: 4 additions & 3 deletions target-lm32/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1015,6 +1015,7 @@ static inline
void gen_intermediate_code_internal(LM32CPU *cpu,
TranslationBlock *tb, bool search_pc)
{
CPUState *cs = CPU(cpu);
CPULM32State *env = &cpu->env;
struct DisasContext ctx, *dc = &ctx;
uint16_t *gen_opc_end;
Expand All @@ -1032,7 +1033,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,

dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->singlestep_enabled = env->singlestep_enabled;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->nr_nops = 0;

if (pc_start & 3) {
Expand Down Expand Up @@ -1077,7 +1078,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,

} while (!dc->is_jmp
&& tcg_ctx.gen_opc_ptr < gen_opc_end
&& !env->singlestep_enabled
&& !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
Expand All @@ -1086,7 +1087,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
gen_io_end();
}

if (unlikely(env->singlestep_enabled)) {
if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
Expand Down
7 changes: 4 additions & 3 deletions target-m68k/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2974,6 +2974,7 @@ static inline void
gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
uint16_t *gen_opc_end;
Expand All @@ -2995,7 +2996,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
dc->singlestep_enabled = env->singlestep_enabled;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
dc->is_mem = 0;
Expand Down Expand Up @@ -3038,14 +3039,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
disas_m68k_insn(env, dc);
num_insns++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
!env->singlestep_enabled &&
!cs->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
num_insns < max_insns);

if (tb->cflags & CF_LAST_IO)
gen_io_end();
if (unlikely(env->singlestep_enabled)) {
if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
gen_flush_cc_op(dc);
Expand Down
8 changes: 5 additions & 3 deletions target-microblaze/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1741,6 +1741,7 @@ static inline void
gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUMBState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
Expand All @@ -1766,7 +1767,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
dc->jmp = JMP_INDIRECT;
}
dc->pc = pc_start;
dc->singlestep_enabled = env->singlestep_enabled;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->cpustate_changed = 0;
dc->abort_at_next_insn = 0;
dc->nr_nops = 0;
Expand Down Expand Up @@ -1859,8 +1860,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
break;
}
}
if (env->singlestep_enabled)
if (cs->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
&& tcg_ctx.gen_opc_ptr < gen_opc_end
&& !singlestep
Expand All @@ -1887,7 +1889,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
}
t_sync_flags(dc);

if (unlikely(env->singlestep_enabled)) {
if (unlikely(cs->singlestep_enabled)) {
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);

if (dc->is_jmp != DISAS_JUMP) {
Expand Down
11 changes: 7 additions & 4 deletions target-mips/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15543,6 +15543,7 @@ static inline void
gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
CPUMIPSState *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
Expand All @@ -15561,7 +15562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
ctx.pc = pc_start;
ctx.saved_pc = -1;
ctx.singlestep_enabled = env->singlestep_enabled;
ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
ctx.tb = tb;
ctx.bstate = BS_NONE;
Expand Down Expand Up @@ -15637,8 +15638,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
break;
}

if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
Expand All @@ -15653,9 +15655,10 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
if (singlestep)
break;
}
if (tb->cflags & CF_LAST_IO)
if (tb->cflags & CF_LAST_IO) {
gen_io_end();
if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
}
if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
} else {
Expand Down
5 changes: 3 additions & 2 deletions target-moxie/translate.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -824,6 +824,7 @@ static inline void
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
CPUState *cs = CPU(cpu);
DisasContext ctx;
target_ulong pc_start;
uint16_t *gen_opc_end;
Expand Down Expand Up @@ -871,7 +872,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
ctx.pc += decode_opc(cpu, &ctx);
num_insns++;

if (env->singlestep_enabled) {
if (cs->singlestep_enabled) {
break;
}

Expand All @@ -880,7 +881,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
}
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);

if (env->singlestep_enabled) {
if (cs->singlestep_enabled) {
tcg_gen_movi_tl(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
Expand Down
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