Senior College Student CS : Computer System Structure & FPGA & RTOS
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ustc
- Hefei Anhui China
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RISC_V-multicycle
RISC_V-multicycle PublicForked from fox6666/RISC_V-multicycle
基于RISC_V指令集架构实现的一个多周期CPU
Verilog 1
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USTCRVSoC
USTCRVSoC PublicForked from WangXuan95/USTC-RVSoC
一个用 SystemVerilog 编写的,RISC-V 架构的 CPU + SoC
SystemVerilog 1
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PipeCNN
PipeCNN PublicForked from fox6666/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
C++
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