firrtl: Add support for yosys' $lut cell

[sahandKashani]

The firrtl backend does not support yosys' $lut cell and emits an error if a techmapped circuit goes through the write_firrtl pass.
Firrtl does not have a native cell type to represent LUTs, so this PR uses the same mechanism currently employed by the verilog backend (shifting the LUT equation to the right by the amount specified by the LUT inputs).

I'm using the following verilog input circuit and yosys script for demonstration purposes, but this pass has also been tested on a floating-point adder:

module test(
  input        in_0,
  input  [3:0] in_1,
  input  [3:0] in_2,
  output [3:0] out_0
);
  assign out_0 = in_0 ? in_1 : in_2;
endmodule

read_verilog test_input.v
hierarchy -check
techmap
abc -lut 4
write_verilog test_lut.v
write_firrtl test_lut.fir

The write_verilog command emits the following:

assign _11_ = 8'hac >> { _00_, _07_, _03_ };
assign _10_ = 8'hca >> { _00_, _02_, _06_ };
assign _09_ = 8'hca >> { _00_, _01_, _05_ };
assign _12_ = 8'hca >> { _00_, _04_, _08_ };

Before this PR, the following error is emitted by the firrtl backend:

7. Executing FIRRTL backend.

7.1. Executing PMUXTREE pass.
ERROR: Cell type not supported: $lut (logic_mux_unsigned64.$abc$79$auto$blifparse.cc:515:parse_blif$80)

After this PR, the following firrtl is output (note that I have shortened the names and aligned them with what the verilog backend emits through write_verilog for brevity below; the abc-generated names are much longer):

_11_ <= bits(dshr(UInt<8>("hac"), cat(_00_, cat(_07_, _03_))), 0, 0)
_10_ <= bits(dshr(UInt<8>("hca"), cat(_00_, cat(_02_, _06_))), 0, 0)
_09_ <= bits(dshr(UInt<8>("hca"), cat(_00_, cat(_01_, _05_))), 0, 0)
_12_ <= bits(dshr(UInt<8>("hca"), cat(_00_, cat(_04_, _08_))), 0, 0)