Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command

[clairexen]

This PR adds "buffered-normalized mode" to RTLIL. In that mode there's a 1:1 relationship between cell ouput ports and wires, and each wire is annotated with a reference to the cell and cell port driving it.

Once in "buffered-normalized mode" calling design->bufNormalize() (or module->bufNormalize()) will ensure that the above condition is met, by adding additional intermediate wires and buffer cells as needed.

This PR also adds a $buf "coarse-grain" buffer cell type, similar in behavior to $pos, but techmap/simplemap/etc is not mapping this buffer type to an array of single-bit buffers. bufNormalize() is adding buffers of that new $buf type. Note that bufNormalize() is very efficient and only looks at the parts of the design that have been changed since the last time bufNormalize() has been run, i.e. it does not require a complete scan over the design.

This PR also adds the bufnorm command for getting the design into and out of "buffered-normalized mode", with more control over the exact type of network of buffers that is being created.

[povik]

Since it should be always possible to reconstruct this data, why not dump it as a comment in the RTLIL output? (Does RTLIL support comments?) And if we do dump it as a comment, maybe we could include it unconditionally and drop the argument to dump_wire.

[povik]

...and drop the other new dump arguments and the option to the pass.

[povik]

This PR also adds a $buf "coarse-grain" buffer cell type, similar in behavior to $pos, but techmap/simplemap/etc is not mapping this buffer type to an array of single-bit buffers.

FWIW that doesn't seem to be the behavior for $pos cells either

yosys/passes/techmap/simplemap.cc

Lines 45 to 53 in 7d30f71

	void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
	{
	RTLIL::SigSpec sig_a = cell->getPort(ID::A);
	RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
	sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
	module->connect(RTLIL::SigSig(sig_y, sig_a));
	}

[widlarizer]

Since setPort may bufNormQueue.insert, a Cell* may survive in bufNormQueue beyond when the underlying cell is removed. Repro: rebase this branch onto main (855ac28), then read_rtlil bug.proc.il; bufnorm -update; opt; bufnorm -update segfaults on my linux machine, where bug.proc.il is

autoidx 16

module \bug

  wire width 32 $procmux$14_Y

  wire $procmux$15_CMP

  wire $auto$bugpoint.cc:258:simplify_something$1

  wire width 32 output 1 $auto$bugpoint.cc:258:simplify_something$3

  wire width 30 $auto$bugpoint.cc:258:simplify_something$4

  wire width 32 $auto$bugpoint.cc:258:simplify_something$5

  wire $delete_wire$6

  wire width 32 \pc$next

  cell $mux $procmux$14
    parameter \WIDTH 32
    connect \Y $procmux$14_Y
    connect \S $procmux$15_CMP
    connect \B 0
    connect \A 32'x
  end

  cell $dff $7
    parameter \WIDTH 32
    parameter \CLK_POLARITY 1
    connect \Q $auto$bugpoint.cc:258:simplify_something$3
    connect \D \pc$next
    connect \CLK $auto$bugpoint.cc:258:simplify_something$1
  end

  connect $procmux$15_CMP $delete_wire$6
  connect \pc$next $procmux$14_Y
end

[whitequark]

oh hey, a new user of bugpoint :D