Support for single bit coarse cells. Option for debug prints. #433
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@rqou Can you review this PR please? Thanks. |
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Apologies, I missed this. I will review this soon. |
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It would be really helpful if this PR added a debug option and a new feature in separate commits. |
nakengelhardt
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Are we there yet? @rqou :D |
cliffordwolf
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Looks mostly fine. One major suggestion, and needs rebasing.
EDIT: Also what @whitequark said
| (cell->type == "$xor" && gt == GateType::Xor); | ||
| } | ||
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| bool is_single_bit(Cell *cell, SigMap sigmap) |
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I think it would be a good idea to call this function from the IsRightType function (rather than modifying all of the call sites). This helps prevent accidentally forgetting to call is_single_bit in a critical location.
| if (debug_verbose) | ||
| { | ||
| log(" Chain head cell is: %s\n", head_cell->name.c_str()); | ||
| log(" Chain head cell Y width: %i\n", GetSize(head_cell->getPort("\\Y"))); |
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Can any of these Y width debug prints ever print a value other than 1? If not, there's no value in having these particular print statements (the other verbose logging is still useful).
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