remove sorts from some optimisation passes

[Ravenslofty]

I was given a test case that is an example of #3713, where changing the name of a variable changed synthesis results. I tracked that down to a handful of design->sort() calls which sort the wires in the design alphabetically; removing them leads to identical synthesis results for the changed names.

This isn't really a fix for #3713, but it does alleviate some of the pain.

[widlarizer]

But there must have been some intention behind these sorts. Avoiding reordering parts of a design before vs after a command seems just about as valid a UX requirement as "a newline doesn't change how my stuff synthesizes"

[Ravenslofty]

Well, based on how the Anlogic latch test produces very different synthesis results on macOS vs Linux, perhaps one of those reasons was to mitigate platform differences.

But from my experiments, Yosys is generally pretty good at preserving the order of things in the network anyway.

[widlarizer]

I don't believe #3713 is as severe as unknown changes to the risk of platform dependent results. Have we previously identified the sources of platform dependent behavior inside yosys so that I could review this PR by verifying whether any apply here?