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Cochin University of Science and Technology
Stars
Functional verification project for the CORE-V family of RISC-V cores.
A Beautiful Private and Secure Desktop Investment Tracking Application
RISC-V Open Source Supervisor Binary Interface
64-bit multicore Linux-capable RISC-V processor
implementation of a 32-bit single-cycle microarchitecture MIPS processor
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
Low-overhead tracing of all Linux kernel-user transitions, for serious performance analysis. Includes kernel patches, loadable module, and post-processing software. Output is HTML/SVG per-CPU-core …
A go-to repository for exploring, learning, and mastering RTL design and verification.
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
FPGA based Vision Transformer accelerator (Harvard CS205)
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
GNU toolchain for RISC-V, including GCC
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …
Curated list of project-based tutorials
Find if the Youtube Thumbnail is a clickbait or not
Contains Solutions and Notes for the Machine Learning Specialization By Stanford University and Deeplearning.ai - Coursera (2022) by Prof. Andrew NG
30 days of JavaScript programming challenge is a step-by-step guide to learn JavaScript programming language in 30 days. This challenge may take more than 100 days, please just follow your own pace…