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deep peace
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deep peace
  • Cochin University of Science and Technology

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Verilog library for ASIC and FPGA designers

Verilog 1,168 285 Updated May 8, 2024

Functional verification project for the CORE-V family of RISC-V cores.

Assembly 432 220 Updated Sep 24, 2024

A Beautiful Private and Secure Desktop Investment Tracking Application

TypeScript 3,919 186 Updated Oct 5, 2024

RISC-V Open Source Supervisor Binary Interface

C 1,004 502 Updated Sep 27, 2024

64-bit multicore Linux-capable RISC-V processor

SystemVerilog 75 10 Updated Sep 12, 2024

Dual-issue RV64IM processor for fun & learning

Verilog 57 6 Updated Jul 4, 2023

32-bit Superscalar RISC-V CPU

Verilog 850 146 Updated Sep 18, 2021

implementation of a 32-bit single-cycle microarchitecture MIPS processor

Verilog 2 Updated Jul 2, 2024

Learn RISC-V

Assembly 13 1 Updated Aug 31, 2024

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

Bluespec 1 Updated Jul 19, 2024

Low-overhead tracing of all Linux kernel-user transitions, for serious performance analysis. Includes kernel patches, loadable module, and post-processing software. Output is HTML/SVG per-CPU-core …

HTML 627 57 Updated Sep 1, 2024

A go-to repository for exploring, learning, and mastering RTL design and verification.

Verilog 3 Updated Sep 10, 2024

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

498 57 Updated Jul 4, 2024

The fastest and safest AV1 encoder.

Assembly 3,702 252 Updated Oct 6, 2024

Modern audio compression for the internet.

C 2,270 606 Updated Oct 4, 2024

FPGA based Vision Transformer accelerator (Harvard CS205)

SystemVerilog 79 7 Updated Dec 11, 2023

FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference

V 106 13 Updated Jun 9, 2023

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。

Verilog 254 61 Updated Sep 14, 2023

lowRISC Style Guides

360 122 Updated Sep 13, 2024

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

SystemVerilog 253 178 Updated Oct 8, 2024

GNU toolchain for RISC-V, including GCC

C 3,462 1,139 Updated Oct 1, 2024

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

C 113 14 Updated Jun 12, 2024
Verilog 1 Updated Sep 24, 2023

Learning golang basics

Go 1 Updated Jun 22, 2021

Curated list of project-based tutorials

199,825 26,073 Updated Aug 15, 2024

Find if the Youtube Thumbnail is a clickbait or not

HTML 1 Updated May 13, 2023

Learning FPGA, yosys, nextpnr, and RISC-V

C++ 2,532 243 Updated May 11, 2024

Contains Solutions and Notes for the Machine Learning Specialization By Stanford University and Deeplearning.ai - Coursera (2022) by Prof. Andrew NG

Jupyter Notebook 3,552 2,284 Updated Sep 29, 2024

30 days of JavaScript programming challenge is a step-by-step guide to learn JavaScript programming language in 30 days. This challenge may take more than 100 days, please just follow your own pace…

JavaScript 42,925 9,968 Updated Aug 19, 2024
Python 2 Updated Oct 27, 2022