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Architecture and Computer Organization II Project: Part Two

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Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
Mantis		Mantis
test_FP		test_FP
test_sencillo_con_NOPs		test_sencillo_con_NOPs
ALU.vhd		ALU.vhd
BReg.vhd		BReg.vhd
Banco_EX.vhd		Banco_EX.vhd
Banco_ID.vhd		Banco_ID.vhd
Banco_MEM.vhd		Banco_MEM.vhd
Banco_WB.vhd		Banco_WB.vhd
Ext_signo.vhd		Ext_signo.vhd
LICENSE		LICENSE
MC_datos.vhd		MC_datos.vhd
MD_cont.vhd		MD_cont.vhd
MD_mas_MC.vhd		MD_mas_MC.vhd
Mantis.cr.mti		Mantis.cr.mti
Mantis.mpf		Mantis.mpf
Mantis.mpf_lock		Mantis.mpf_lock
Mips_segmentado_2018.vhd		Mips_segmentado_2018.vhd
Mips_segmentado_2018.vhd.bak		Mips_segmentado_2018.vhd.bak
README.md		README.md
Test_MD.vhd		Test_MD.vhd
UA.vhd		UA.vhd
UC_MC.vhd		UC_MC.vhd
UC_MC.vhd.bak		UC_MC.vhd.bak
UC_Mips.vhd		UC_Mips.vhd
UD.vhd		UD.vhd
add_Fp_trst.vhd		add_Fp_trst.vhd
adder32.vhd		adder32.vhd
bits_shifter.vhd		bits_shifter.vhd
counter.vhd		counter.vhd
counter_2bits.vhd		counter_2bits.vhd
design.do		design.do
design2.do		design2.do
design3.do		design3.do
design4.do		design4.do
fpadd.vhd		fpadd.vhd
leeme.txt		leeme.txt
memoriaRAM_I_ejemplo.vhd		memoriaRAM_I_ejemplo.vhd
memoriaRAM_enable.vhd		memoriaRAM_enable.vhd
mux2_1.vhd		mux2_1.vhd
mux2_5bits.vhd		mux2_5bits.vhd
mux4_1_32bits.vhd		mux4_1_32bits.vhd
ondaV0.do		ondaV0.do
ondaV1.do		ondaV1.do
ondaV10.do		ondaV10.do
ondaV11.do		ondaV11.do
ondaV2.do		ondaV2.do
ondaV3.do		ondaV3.do
ondaV4.do		ondaV4.do
ondaV5.do		ondaV5.do
ondaV6.do		ondaV6.do
ondaV7.do		ondaV7.do
ondaV8.do		ondaV8.do
ondaV9.do		ondaV9.do
prova1_d.vhd		prova1_d.vhd
prova1_i.vhd		prova1_i.vhd
pruebas.txt		pruebas.txt
reg32.vhd		reg32.vhd
reg4.vhd		reg4.vhd
reg7.vhd		reg7.vhd
tcl_stacktrace.txt		tcl_stacktrace.txt
testbench_MD_mas_MC_alumnos.vhd		testbench_MD_mas_MC_alumnos.vhd
testbench_Mips.vhd		testbench_Mips.vhd
vish_stacktrace.vstf		vish_stacktrace.vstf
vsim.wlf		vsim.wlf