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[RISC-V] Fix invalid operand register in the emitted addition/subtraction code #102074

Merged
merged 30 commits into from
May 27, 2024
Merged

[RISC-V] Fix invalid operand register in the emitted addition/subtraction code #102074

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f2d7eb1
[RISC-V] Added sext_w pseudoinstruction
Bajtazar May 9, 2024
cf7afe4
[RISC-V] Inserted INS_sext_w pseudoinstruction
Bajtazar May 9, 2024
e962811
[RISC-V] Started implementing new overflow logic
Bajtazar May 9, 2024
836f439
[RISC-V] Finished preliminar implementation of bound checks
Bajtazar May 10, 2024
bcdb4a4
[RISC-V] Fixed invalid 32-bit instruction
Bajtazar May 10, 2024
3e3b72f
[RISC-V] Fixed 32-bit addition overflow check assert
Bajtazar May 10, 2024
685f72e
[RISC-V] More fixes in emitter
Bajtazar May 10, 2024
37ed8d2
[RISC-V] Additional fixes
Bajtazar May 10, 2024
71f9c49
[RISC-V] Fixed triple same register problem in emitInsTernary additio…
Bajtazar May 10, 2024
a5d29d8
[RISC-V] Added sext.w to disassembler
Bajtazar May 10, 2024
c6614fa
[RISC-V] Added comments
Bajtazar May 10, 2024
971b36f
[RISC-V] Formatted code
Bajtazar May 10, 2024
4e0264b
[RISC-V] Fixed bug
Bajtazar May 10, 2024
3d0ba8e
[RISC-V] Fixed other bug
Bajtazar May 10, 2024
807acfc
[RISC-V] Fixed bug causing the int32's version to never be emitted
Bajtazar May 10, 2024
4316263
[RISC-V] Fixed assert
Bajtazar May 10, 2024
b841e3c
[RISC-V] Improved comment
Bajtazar May 10, 2024
f82a853
[RISC-V] Fixed comment
Bajtazar May 10, 2024
1f5dfa9
Merge branch 'main' into riscv-fix-overflow-infinite-loop
Bajtazar May 10, 2024
965be5a
[RISC-V] Fixed temp reg acquiring
Bajtazar May 10, 2024
b34f37d
[RISC-V] Removed asserts
Bajtazar May 10, 2024
4371f04
Fixed NodeInternalRegister's GetSingle method's comment
Bajtazar May 10, 2024
ad89ff5
[RISC-V] Revoked more changes
Bajtazar May 14, 2024
a2cdb16
[RISC-V] Revoked more changes
Bajtazar May 14, 2024
a5c582f
[RISC-V] Embedded sext_w into codegen
Bajtazar May 14, 2024
9078647
[RISC-V] Fixed some comments
Bajtazar May 14, 2024
7b24b88
[RISC-V] Added additional comment
Bajtazar May 14, 2024
6a6dc82
[RISC-V] Improvements
Bajtazar May 14, 2024
06dbd79
[RISC-V] Added old comment
Bajtazar May 14, 2024
e464442
Merge branch 'main' into riscv-fix-overflow-infinite-loop
Bajtazar May 14, 2024
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[RISC-V] Added old comment
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@Bajtazar
Bajtazar committed May 14, 2024
commit 06dbd79bcb58e885439abfe89035c1d891290b29
2 changes: 2 additions & 0 deletions src/coreclr/jit/emitriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5009,6 +5009,8 @@ regNumber emitter::emitInsTernary(instruction ins, emitAttr attr, GenTree* dst,

/*
Check if A = B + C
ADD : A = B + C
SUB : B = A - C
In case of addition:
dst = src1 + src2
A = dst
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