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ARM64 - Emitting msub instruction #66621

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merged 7 commits into from
Apr 12, 2022
Merged

ARM64 - Emitting msub instruction #66621

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09dc7e3
Emitting MSUB for ARM64
TIHan Mar 14, 2022
0247254
Update codegenarm64.cpp
TIHan Mar 14, 2022
ff8ee6f
Updated comments
TIHan Mar 14, 2022
39d098c
Formatting
TIHan Mar 15, 2022
f006f8e
Combining some logic for GT_MADD and GT_MSUB
TIHan Mar 15, 2022
1acab50
Merge remote-tracking branch 'upstream/main' into arm64-msub
TIHan Apr 9, 2022
4655c4f
Can only use gtOverflow after checking to see if it's a valid operato…
TIHan Apr 9, 2022
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Combining some logic for GT_MADD and GT_MSUB
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@TIHan
TIHan committed Mar 15, 2022
commit f006f8e37e763f0117453c79a4733039f1888a68
86 changes: 43 additions & 43 deletions src/coreclr/jit/lowerarmarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1633,59 +1633,59 @@ void Lowering::ContainCheckBinary(GenTreeOp* node)
CheckImmedAndMakeContained(node, op2);

#ifdef TARGET_ARM64
// Find "a * b + c" or "c + a * b" in order to emit MADD/MSUB
if (comp->opts.OptimizationEnabled() && varTypeIsIntegral(node) && !node->isContained() && node->OperIs(GT_ADD) &&
!node->gtOverflow() && (op1->OperIs(GT_MUL) || op2->OperIs(GT_MUL)))
if (comp->opts.OptimizationEnabled() && varTypeIsIntegral(node) && !node->isContained() && !node->gtOverflow())
{
GenTree* mul;
GenTree* c;
if (op1->OperIs(GT_MUL))
// Find "a * b + c" or "c + a * b" in order to emit MADD/MSUB
if (node->OperIs(GT_ADD) && (op1->OperIs(GT_MUL) || op2->OperIs(GT_MUL)))
{
mul = op1;
c = op2;
}
else
{
mul = op2;
c = op1;
}

GenTree* a = mul->gtGetOp1();
GenTree* b = mul->gtGetOp2();

if (!mul->isContained() && !mul->gtOverflow() && !a->isContained() && !b->isContained() && !c->isContained() &&
varTypeIsIntegral(mul))
{
if (a->OperIs(GT_NEG) && !a->gtGetOp1()->isContained() && !a->gtGetOp1()->IsRegOptional())
GenTree* mul;
GenTree* c;
if (op1->OperIs(GT_MUL))
{
// "-a * b + c" to MSUB
MakeSrcContained(mul, a);
mul = op1;
c = op2;
}
if (b->OperIs(GT_NEG) && !b->gtGetOp1()->isContained())
else
{
// "a * -b + c" to MSUB
MakeSrcContained(mul, b);
mul = op2;
c = op1;
}
// If both 'a' and 'b' are GT_NEG - MADD will be emitted.

node->ChangeOper(GT_MADD);
MakeSrcContained(node, mul);
}
}
GenTree* a = mul->gtGetOp1();
GenTree* b = mul->gtGetOp2();

// Find "a - b * c" in order to emit MSUB
if (comp->opts.OptimizationEnabled() && varTypeIsIntegral(node) && !node->isContained() && node->OperIs(GT_SUB) &&
!node->gtOverflow() && op2->OperIs(GT_MUL) && !op2->isContained() && !op2->gtOverflow() &&
varTypeIsIntegral(op2))
{
GenTree* a = op1;
GenTree* b = op2->gtGetOp1();
GenTree* c = op2->gtGetOp2();
if (!mul->isContained() && !mul->gtOverflow() && !a->isContained() && !b->isContained() &&
!c->isContained() && varTypeIsIntegral(mul))
{
if (a->OperIs(GT_NEG) && !a->gtGetOp1()->isContained() && !a->gtGetOp1()->IsRegOptional())
{
// "-a * b + c" to MSUB
MakeSrcContained(mul, a);
}
if (b->OperIs(GT_NEG) && !b->gtGetOp1()->isContained())
{
// "a * -b + c" to MSUB
MakeSrcContained(mul, b);
}
// If both 'a' and 'b' are GT_NEG - MADD will be emitted.

if (!a->isContained() && !b->isContained() && !c->isContained())
node->ChangeOper(GT_MADD);
MakeSrcContained(node, mul);
}
}
// Find "a - b * c" in order to emit MSUB
else if (node->OperIs(GT_SUB) && op2->OperIs(GT_MUL) && !op2->isContained() && !op2->gtOverflow() &&
varTypeIsIntegral(op2))
{
node->ChangeOper(GT_MSUB);
MakeSrcContained(node, op2);
GenTree* a = op1;
GenTree* b = op2->gtGetOp1();
GenTree* c = op2->gtGetOp2();

if (!a->isContained() && !b->isContained() && !c->isContained())
{
node->ChangeOper(GT_MSUB);
MakeSrcContained(node, op2);
}
}
}

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