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Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127

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merged 33 commits into from
Nov 27, 2023
Merged

Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127

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55731b4
Add insEncodeReg* methods
a74nh Nov 22, 2023
90fb3de
Add Arm64 encodings for 3A groups
a74nh Nov 20, 2023
15ee2fc
Remove isSveRegister
a74nh Nov 22, 2023
b7490a0
Split ALL_ARM64_EMITTER_UNIT_TESTS into subsets
a74nh Nov 22, 2023
473483c
AD, AE, AN
a74nh Nov 22, 2023
b4687d4
Merge remote-tracking branch 'origin' into SVE_AA_3A_4_github
a74nh Nov 23, 2023
c5d82cd
Remove REG_PREDICATE_LOW_FIRST
a74nh Nov 23, 2023
4461ecb
Fix sve_ins_offset
a74nh Nov 23, 2023
f93a4f6
Add IF_SVE_AO_3A, including INS_OPTS_SCALABLE_WIDE_
a74nh Nov 23, 2023
d755ab7
Add IF_SVE_CM_3A
a74nh Nov 23, 2023
2dcd8e6
Add IF_SVE_CN_3A, including INS_OPTS_SCALABLE_TO_SIMD_
a74nh Nov 23, 2023
ba57782
IF_SVE_CO_3A and INS_OPTS_SCALABLE_n_TO_SCALAR
a74nh Nov 23, 2023
0d958e0
Rename INS_OPTS_SCALABLE_TO_SIMD_
a74nh Nov 23, 2023
f0bf5ca
Add IF_SVE_EP_3A
a74nh Nov 23, 2023
0477f12
Add IF_SVE_ER_3A
a74nh Nov 23, 2023
64ac5a6
Add IF_SVE_ET_3A
a74nh Nov 23, 2023
d88891a
Fix formatting
a74nh Nov 24, 2023
89e8ccd
Add IF_SVE_EU_3A
a74nh Nov 24, 2023
947e76c
IF_SVE_EU_3A
a74nh Nov 24, 2023
6056790
Add IF_SVE_HJ_3A
a74nh Nov 24, 2023
af7b818
Add IF_SVE_HJ_3A
a74nh Nov 24, 2023
819ff13
Add PredicateType
a74nh Nov 24, 2023
9c06fe7
Remove tests unsupported by capstone
a74nh Nov 24, 2023
7b74dc6
Fix formatting
a74nh Nov 24, 2023
5e9dad8
Comment out unit test define
a74nh Nov 24, 2023
889c909
Add parentheses
a74nh Nov 24, 2023
1e3e98e
Fix fadda predicate and comment typos
a74nh Nov 27, 2023
f2c714b
Fix formatting
a74nh Nov 27, 2023
96271ae
Better commenting + fix up errors found
a74nh Nov 27, 2023
2f763f1
Better descriptions for insOpts functions
a74nh Nov 27, 2023
11d38ba
Add latencies
a74nh Nov 27, 2023
cffafad
Fix formatting
a74nh Nov 27, 2023
15a5fe8
Add emitDispLowPredicateReg
a74nh Nov 27, 2023
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Add IF_SVE_AO_3A, including INS_OPTS_SCALABLE_WIDE_
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@a74nh
a74nh committed Nov 23, 2023
commit f93a4f698b6a3d171fb1440ed4ff45569090bf0a
4 changes: 4 additions & 0 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10148,6 +10148,10 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V5, REG_P5, REG_V6, INS_OPTS_SCALABLE_B); // IF_SVE_AN_3A /* LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lsrr, EA_SCALABLE, REG_V15, REG_P4, REG_V17, INS_OPTS_SCALABLE_S); // IF_SVE_AN_3A /* LSRR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */

theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V4, REG_P3, REG_V24, INS_OPTS_SCALABLE_WIDE_B); // IF_SVE_AO_3A /* ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D */
theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_P7, REG_V3, INS_OPTS_SCALABLE_WIDE_H); // IF_SVE_AO_3A /* LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D */
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_WIDE_S); // IF_SVE_AO_3A /* LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D */

#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
Expand Down
50 changes: 40 additions & 10 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -948,7 +948,6 @@ void emitter::emitInsSanityCheck(instrDesc* id)
case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
case IF_SVE_AE_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated)
case IF_SVE_AN_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by vector (predicated)
case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector
case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar
case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register
Expand Down Expand Up @@ -976,6 +975,15 @@ void emitter::emitInsSanityCheck(instrDesc* id)
assert(isScalableVectorSize(elemsize)); // xx
break;

case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
elemsize = id->idOpSize();
assert(insOptsScalableWide(id->idInsOpt()));
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isLowPredicateRegister(id->idReg2())); // ggg
assert(isVectorRegister(id->idReg3())); // mmmmm
assert(isScalableVectorSize(elemsize)); // xx
break;

default:
printf("unexpected format %s\n", emitIfName(id->idInsFmt()));
assert(!"Unexpected format");
Expand Down Expand Up @@ -8136,11 +8144,8 @@ void emitter::emitIns_R_R_R(
fmt = IF_SVE_AE_3A;
break;

case INS_sve_asr:
case INS_sve_asrr:
case INS_sve_lsl:
case INS_sve_lslr:
case INS_sve_lsr:
case INS_sve_lsrr:
assert(isVectorRegister(reg1));
assert(isLowPredicateRegister(reg2));
Expand All @@ -8149,8 +8154,24 @@ void emitter::emitIns_R_R_R(
fmt = IF_SVE_AN_3A;
break;

case INS_sve_asr:
case INS_sve_lsl:
case INS_sve_lsr:
assert(isVectorRegister(reg1));
assert(isLowPredicateRegister(reg2));
assert(isVectorRegister(reg3));
if (insOptsScalable(opt))
{
fmt = IF_SVE_AN_3A;
}
else
{
assert(insOptsScalableWide(opt));
fmt = IF_SVE_AO_3A;
}
break;

//TODO in this PR....
// case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
// case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector
// case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar
// case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register
Expand Down Expand Up @@ -11785,15 +11806,15 @@ void emitter::emitIns_Call(EmitCallType callType,
{
return 0x00C00000; // set the bit at location 23 and 22
}
else if (opt == INS_OPTS_SCALABLE_S)
else if (opt == INS_OPTS_SCALABLE_S || opt == INS_OPTS_SCALABLE_WIDE_S)
{
return 0x00800000; // set the bit at location 23
}
else if (opt == INS_OPTS_SCALABLE_H)
else if (opt == INS_OPTS_SCALABLE_H || opt == INS_OPTS_SCALABLE_WIDE_H)
{
return 0x00400000; // set the bit at location 22
}
assert(opt == INS_OPTS_SCALABLE_B);
assert(opt == INS_OPTS_SCALABLE_B || opt == INS_OPTS_SCALABLE_WIDE_B);
return 0x00000000;
}

Expand Down Expand Up @@ -14231,7 +14252,7 @@ void emitter::emitDispReg(regNumber reg, emitAttr attr, bool addComma)
//
void emitter::emitDispSveReg(regNumber reg, insOpts opt, bool addComma)
{
assert(insOptsScalable(opt));
assert(insOptsScalable(opt) || insOptsScalableWide(opt));
assert(isVectorRegister(reg));
printf(emitSveRegName(reg));
emitDispArrangement(opt);
Expand Down Expand Up @@ -14361,6 +14382,7 @@ void emitter::emitDispArrangement(insOpts opt)
str = "16b";
break;
case INS_OPTS_SCALABLE_B:
case INS_OPTS_SCALABLE_WIDE_B:
str = "b";
break;
case INS_OPTS_4H:
Expand All @@ -14370,6 +14392,7 @@ void emitter::emitDispArrangement(insOpts opt)
str = "8h";
break;
case INS_OPTS_SCALABLE_H:
case INS_OPTS_SCALABLE_WIDE_H:
str = "h";
break;
case INS_OPTS_2S:
Expand All @@ -14379,6 +14402,7 @@ void emitter::emitDispArrangement(insOpts opt)
str = "4s";
break;
case INS_OPTS_SCALABLE_S:
case INS_OPTS_SCALABLE_WIDE_S:
str = "s";
break;
case INS_OPTS_1D:
Expand Down Expand Up @@ -15958,7 +15982,6 @@ void emitter::emitDispInsHelp(
case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
case IF_SVE_AE_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated)
case IF_SVE_AN_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by vector (predicated)
case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector
case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar
case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register
Expand All @@ -15975,6 +15998,13 @@ void emitter::emitDispInsHelp(
emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm
break;

case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd
emitDispPredicateReg(id->idReg2(), true, true); // ggg
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd
emitDispSveReg(id->idReg3(), INS_OPTS_SCALABLE_D, false); // mmmmm
break;

default:
printf("unexpected format %s", emitIfName(id->idInsFmt()));
assert(!"unexpectedFormat");
Expand Down
5 changes: 5 additions & 0 deletions src/coreclr/jit/emitarm64.h
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Expand Up @@ -853,6 +853,11 @@ inline static bool insOptsScalableWords(insOpts opt)
return ((opt == INS_OPTS_SCALABLE_S || opt == INS_OPTS_SCALABLE_D));
}

inline static bool insOptsScalableWide(insOpts opt)
{
return ((opt == INS_OPTS_SCALABLE_WIDE_B || opt == INS_OPTS_SCALABLE_WIDE_H || opt == INS_OPTS_SCALABLE_WIDE_S));
}

static bool isValidImmCond(ssize_t imm);
static bool isValidImmCondFlags(ssize_t imm);
static bool isValidImmCondFlagsImm5(ssize_t imm);
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/instr.h
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Expand Up @@ -273,6 +273,10 @@ enum insOpts : unsigned
INS_OPTS_SCALABLE_S,
INS_OPTS_SCALABLE_D,

INS_OPTS_SCALABLE_WIDE_B,
INS_OPTS_SCALABLE_WIDE_H,
INS_OPTS_SCALABLE_WIDE_S,

INS_OPTS_MSL, // Vector Immediate (shifting ones variant)

INS_OPTS_S_TO_4BYTE, // Single to INT32
Expand Down