This repository is a template for project 2.2 that takes you through:
- Building an edge detector
- Building a seven segment driver
- Counting edges
- State machines
This repo is part of the Zero to ASIC course and licensed with Apache 2.
- Verilog cheatsheet: https://marceluda.github.io/rp_dummy/EEOF2018/Verilog_Cheat_Sheet.pdf
- Clock domain crossing: http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
- Flip flops and metastability: https://www.youtube.com/watch?v=5PRuPVIjEcs
- VHDL resources: https://docs.google.com/document/d/1RAQWjmxpJndlEJdLWXK8irIqWuYTstqu7pU3tOIFccc/edit
- Charles Eric LaForest design elements guide: http://fpgacpu.ca/fpga/index.html